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EMC2106 Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
PRODUCT FEATURES
General Description
The EMC2106 is an SMBus compliant fan controller with up to five (up to 4 external and 1 internal) temperature channels. The fan drivers can be operated using two methods each with two modes. The methods include an RPM based Fan Speed Control Algorithm and a direct drive setting. The modes include manually programming the desired settings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. The temperature monitors offer 1C accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors. The EMC2106 also includes a hardware programmable temperature limitS and dedicated system shutdown output for thermal protection of critical circuitry. Datasheet
Features
Two Programmable Fan Control circuits.
-- -- -- -- -- -- 4-wire fan compatible High speed PWM (26khz) Low speed PWM (9.5Hz - 2240Hz) 600mA, 5V, High Side Fan Driver Optional detection of aging fans 1mA Linear DAC Fan Driver
RPM based fan control algorithm
-- 2% accuracy from 500RPM to 16k RPM
Temperature Look-Up Table
-- -- -- -- Allows programmed fan response to temperature 1 to 4 thermal zones to control each fan driver Controls fan speed or drive setting Allows externally generated temperature data to control fan drivers including two DTS channels
Up to Four External Temperature Channels
-- Designed to support 45nm, 60nm, and 90nm CPUs -- Automatically detects and supports CPUs requiring the BJT or Transistor models -- Resistance error correction -- 1C accurate (60C to 100C) -- 0.125C resolution -- Detects fan aging and variation
Applications
Notebook Computers Embedded Applications Projectors Industrial and Networking Equipment
Three dedicated comparator outputs for External Diode 1, External Diode 2, and External Diode 3 (OVERT1#, OVERT2#, OVERT3#) Up to three thermistor compatible voltage inputs Hardware Programmable Thermal Shutdown Temperature
-- Cannot be altered by software -- 60C to 122C Range or 92C to 154C Range
Programmable High and Low Limits for all channels 3.3V Supply Voltage SMBus 2.0 Compliant
-- 2 selectable SMBus addresses -- SMBus Alert compatible -- Option to load register set from external EEPROM
Available in 28-pin QFN package - Lead Free RoHS compliant (5mm x 5mm)
SMSC EMC2106
DATASHEET
Revision 1.72 (11-01-07)
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
ORDER NUMBER:
ORDERING NUMBER EMC2106-1-DZK PACKAGE 28 pin QFN (Lead-Free RoHS compliant) FEATURES Two independent fan drivers (one High Side, one Linear), up to 4 external diode measurement channels, one Critical / Thermal Shutdown input
80 ARKAY DRIVE, HAUPPAUGE, NY 11788 (631) 435-6000, FAX (631) 273-3123 Copyright (c) 2007 SMSC or its subsidiaries. All rights reserved. Circuit diagrams and other information relating to SMSC products are included as a means of illustrating typical applications. Consequently, complete information sufficient for construction purposes is not necessarily given. Although the information has been checked and is believed to be accurate, no responsibility is assumed for inaccuracies. SMSC reserves the right to make changes to specifications and product descriptions at any time without notice. Contact your local SMSC sales office to obtain the latest specifications before placing your product order. The provision of this information does not convey to the purchaser of the described semiconductor devices any licenses under any patent rights or other intellectual property rights of SMSC or others. All sales are expressly conditional on your agreement to the terms and conditions of the most recently dated version of SMSC's standard Terms of Sale Agreement dated before the date of your order (the "Terms of Sale Agreement"). The product may contain design defects or errors known as anomalies which may cause the product's functions to deviate from published specifications. Anomaly sheets are available upon request. SMSC products are not designed, intended, authorized or warranted for use in any life support or other application where product failure could cause or contribute to personal injury or severe property damage. Any and all such uses without prior written approval of an Officer of SMSC and further testing and/or modification will be fully at the risk of the customer. Copies of this document or other SMSC literature, as well as the Terms of Sale Agreement, may be obtained by visiting SMSC's website at http://www.smsc.com. SMSC is a registered trademark of Standard Microsystems Corporation ("SMSC"). Product names and company names are the trademarks of their respective holders. SMSC DISCLAIMS AND EXCLUDES ANY AND ALL WARRANTIES, INCLUDING WITHOUT LIMITATION ANY AND ALL IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, TITLE, AND AGAINST INFRINGEMENT AND THE LIKE, AND ANY AND ALL WARRANTIES ARISING FROM ANY COURSE OF DEALING OR USAGE OF TRADE. IN NO EVENT SHALL SMSC BE LIABLE FOR ANY DIRECT, INCIDENTAL, INDIRECT, SPECIAL, PUNITIVE, OR CONSEQUENTIAL DAMAGES; OR FOR LOST DATA, PROFITS, SAVINGS OR REVENUES OF ANY KIND; REGARDLESS OF THE FORM OF ACTION, WHETHER BASED ON CONTRACT; TORT; NEGLIGENCE OF SMSC OR OTHERS; STRICT LIABILITY; BREACH OF WARRANTY; OR OTHERWISE; WHETHER OR NOT ANY REMEDY OF BUYER IS HELD TO HAVE FAILED OF ITS ESSENTIAL PURPOSE, AND WHETHER OR NOT SMSC HAS BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES.
Revision 1.72 (11-01-07)
2
SMSC EMC2106
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table of Contents
Chapter 1 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Chapter 2 Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Chapter 3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1 3.2 3.3 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 SMBus Electrical Specifications (client mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 EEPROM Loader Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Chapter 4 Communications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 System Management Bus Interface Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Write Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Read Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Send Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Receive Byte. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Alert Response Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Address . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . SMBus Time-out . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Programming from EEPROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 20 21 21 21 21 22 22 22
Chapter 5 Product Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
5.1 Critical/Thermal Shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.1 SHDN_SEL Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1.2 TRIP_SET / VIN4 Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Modes of Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . High Side Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3.1 Over Current Limit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Linear DAC Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Fan Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Control Look-Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.1 Programming the Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.6.2 DTS Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RPM based Fan Speed Control Algorithm (FSC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.7.1 Programming the RPM Based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . Tachometer Measurement . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.1 Stalled Fan . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.2 32kHz Clock Source . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.8.3 Aging Fan or Invalid Drive Detection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Watchdog Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Internal Thermal Shutdown (TSD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.1 Dynamic Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.2 Resistance Error Correction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.3 Beta Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.14.4 Digital Averaging . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Thermistor Support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Diode Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.16.1 Diode Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3
5.2 5.3 5.4 5.5 5.6
5.7 5.8
5.9 5.10 5.11 5.12 5.13 5.14
5.15 5.16
25 26 26 28 29 29 30 30 30 31 32 32 34 34 34 35 35 35 36 37 38 38 38 38 39 39 39 39 39 40
SMSC EMC2106
Revision 1.72 (11-01-07)
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
5.17 5.18 5.19
GPIOs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Over Limit Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Chapter 6 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
6.1 6.2 6.3 6.4 6.5 6.6 6.7 6.8 6.9 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 6.29 6.30 6.31 6.32 6.33 6.34 6.35 6.36 6.37 6.38 6.39 6.40 6.41 6.42 6.43 6.44 6.45 6.46 6.47 6.48 Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.1.1 Lock Entries . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical/Thermal Shutdown Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pushed Temperature Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Beta Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Critical Temperature Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Status Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Error Status Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6.13.1 Tcrit Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM 3 and 4 Divide Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM 3 Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM 4 Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Setting Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . PWM 1 and 2 Divide Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Configuration 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Minimum Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Fan Drive Fail Band Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Look Up Table 2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Muxed Pin Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO / PWM Pin Output Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Output Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Interrupt Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GPIO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Software Lock Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product Features Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Manufacturer ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4
42 53 54 55 56 56 57 58 59 59 60 61 62 63 63 64 64 65 66 66 67 67 68 68 69 70 70 72 74 75 76 77 77 78 78 79 80 81 83 84 86 86 86 87 87 87 88 88 89 89
Revision 1.72 (11-01-07)
SMSC EMC2106
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
6.49
Revision Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Chapter 7 Package Drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
7.1 QFN 28-pin 5mm x 5mm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Appendix A Thermistors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
A.1 Thermistor Look Up Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Appendix B Look Up Table Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
B.1 B.2 B.3 Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Example #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
Appendix C RPM to Tachometer Count Look Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
C.1 1k RPM Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
SMSC EMC2106
5
Revision 1.72 (11-01-07)
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
List of Figures
Figure 1.1 Figure 2.1 Figure 4.1 Figure 5.1 Figure 5.2 Figure 5.3 Figure 5.4 Figure 5.5 Figure 5.6 Figure 5.7 Figure 6.1 Figure 7.1 Figure A.1 EMC2106 Block Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 EMC2106 Pin Diagram (28 pin QFN). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 SMBus Timing Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 System Diagram of EMC2106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 EMC2106 Critical/Thermal Shutdown Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Fan Control Look-Up Table Example. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 RPM based Fan Speed Control Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Spin Up Routine . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Ramp Rate Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Diode Connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 LOWDRIVE Supported Drive Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 EMC2106 28-Pin 5x5mm QFN Package Outline and Parameters . . . . . . . . . . . . . . . . . . . . 90 "Low Side" Thermistor Connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
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SMSC EMC2106
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
List of Tables
Table 2.1 Pin Description for EMC2106 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 2.2 Pin Types. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.2 Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.3 SMBus Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 3.4 EEPROM Loader Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.1 Protocol Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.2 Write Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.3 Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.4 Send Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.5 Receive Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.6 Alert Response Address Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.7 ADDR_SEL Pin Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 4.8 Block Read Byte Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.1 SHDN_SEL Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.2 TRIP_SET Resistor Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.3 Fan Controls Active for Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 5.4 Dynamic Averaging Behavior . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.1 EMC2106 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.2 Temperature Data Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.3 Temperature Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.4 Critical/Thermal Shutdown Temperature Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.5 Critical / Thermal Shutdown Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.6 Pushed Temperature Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.7 TripSet Voltage Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.8 Beta Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.9 Beta Compensation Look Up Table. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.10 REC Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.11 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.12 Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.13 Configuration 2 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.14 Fault Queue . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.15 Conversion Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.16 Configuration 3 Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.17 Interrupt Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.18 Error Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.19 Fan Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.20 Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.21 Fan Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.22 PWM Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.23 PWM Base Frequency Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.24 PWM_BASEx[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.25 PWM Divide Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.26 PWM 3 Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.27 PWM 4 Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.28 Limit Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.29 Fan Driver Setting Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.30 PWM 1 and 2 Divide Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.31 Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.32 Range Decode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.33 Minimum Edges for Fan Rotation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.34 Update Time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Table 6.35 Fan Configuration 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
SMSC EMC2106 7
11 13 15 15 18 19 20 20 21 21 21 21 22 23 26 27 29 38 42 54 55 55 55 56 56 57 57 58 59 59 60 61 61 61 62 63 64 64 65 66 66 67 67 67 68 68 69 70 70 71 71 72 72
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.36 Derivative Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 6.37 Error Range Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Table 6.38 Gain Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 6.39 Gain Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 Table 6.40 Fan Spin Up Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 6.41 DRIVE_FAIL_CNT[1:0] Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 6.42 Spin Level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Table 6.43 Spin Time. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 6.44 Fan Step Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 Table 6.45 Minimum Fan Drive Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 6.46 Valid TACH Count Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77 Table 6.47 Fan Drive Fail Band Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 6.48 TACH Target Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 Table 6.49 TACH Reading Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 Table 6.50 Look Up Table Configuration Registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 Table 6.51 TEMP3_CFG Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 6.52 TEMP4_CFG Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 6.53 Look Up Table 1 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Table 6.54 Look Up Table2 Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 Table 6.55 Muxed Pin Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 Table 6.56 GPIO5_CFG[1:0] Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 6.57 GPIO4_CFG[1:0] Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Table 6.58 GPIO Direction Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 6.59 GPIO / PWM Pin Output Configuration Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 6.60 GPIO Input Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Table 6.61 GPIO Output Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 6.62 GPIO Interrupt Enable Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 6.63 GPIO Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Table 6.64 Software Lock Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 6.65 Product Features Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Table 6.66 SHDN_SEL Bit Decode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 6.67 Product ID Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 6.68 Manufacturer ID Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table 6.69 Revision Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 Table A.1 "Low Side" Thermistor Look Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 Table A.2 Inverted Thermistor Look Up Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Table B.1 Look Up Table Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 Table B.2 Look Up Table Example #1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table B.3 Fan Speed Control Table Example #1. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 Table B.4 Fan Speed Determination for Example #1 (using settings in Table B.3) . . . . . . . . . . . . . . . . . 97 Table B.5 Look Up Table Example #2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table B.6 Fan Speed Control Table Example #2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 Table B.7 Fan Speed Determination for Example #2 (using settings in Table B.6) . . . . . . . . . . . . . . . . . 99 Table B.8 Look Up Table Example #3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table B.9 Fan Speed Control Table Example #3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Table B.10 Fan Speed Determination for Example #3 (using settings in Table B.9) . . . . . . . . . . . . . . . . 101 Table C.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM). . . . . . . . . . . . . . . . . . . . . 102
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SMSC EMC2106
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Chapter 1 Block Diagram
VIN2*
TRIP_SET* DP1 DN1 DP2 DN2 DN4 / DP3* DP4 / DN3* Antiparallel diode Configuration Internal Temp Diode Thermal Shutdown Logic
VIN1*
VIN3*
SYS_SHDN#
SHDN_SEL
ADDR_SEL SMCLK Temp Limit Registers SMBus Slave Protocol SMDATA ALERT# OVERT1#* OVERT2#* OVERT3#*
External Temp Diodes Analog Mux
11 bit ADC
Temp Registers
PWM1* PWM2* PWM3* PWM4* TACH1 TACH2* CLK_IN* VDD_5V FAN_OUT Tachs High Side Fan Driver PWM Drivers Lookup Table / RPM Control Reference GPIOs
GPIO6 GPIO5* GPIO4* GPIO3* GPIO2* GPIO1* VREF*
DAC
* denotes multiple pin functions
DAC2*
Figure 1.1 EMC2106 Block Diagram
SMSC EMC2106
9
Revision 1.72 (11-01-07)
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Chapter 2 Pin Description
DP3 / DN4 / VREF_T3
ADDR_SEL
DN3 / DP4 / VIN3
DP2 / VREF_T2
28
27
26
25
24
23
22 21 20 19
DN1 / VIN1 DP1 / VREF_T1 GND VDD OVERT3# / GPIO5 / PWM4 ALERT# CLK_IN / GPIO1
1 2 3 4 5 6 7 10 11 12 13 14 8 9 EMC2106 28-QFN 5mm x 5mm
SHDN_SEL
DN2 / VIN2
DAC2
TRIP_SET / VIN4 VDD_5V VDD_5V FAN_OUT FAN_OUT OVERT1# / PWM1 TACH1
18 17 16 15
SYS_SHDN#
SMDATA
PWM2 / GPIO3
OVERT2# / GPIO4 / PWM3
Figure 2.1 EMC2106 Pin Diagram (28 pin QFN)
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TACH2 / GPIO2
SMCLK
GPIO6
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Table 2.1 Pin Description for EMC2106 PIN NUMBER EMC2106
PIN NAME
PIN FUNCTION DN1 - Negative (cathode) analog input for External Diode 1 (default)
PIN TYPE AIO (2V) AI (2V) AIO (2V) AO (2V) Power Power OD (5V) DI (5V) DO OD (5V) OD (5V) DO OD (5V) DI (5V) DI (5V) DO OD (5V)
1
DN1 / VIN1 VIN1 - General Voltage input to be used with a thermistor DP1 - Positive (anode) analog input for External Diode 1 (default)
2
DP1 / VREF_T1 VREF_T1 - Reference output for use with a thermistor and to drive VIN1
3 4
GND VDD
Ground Connection Power Supply OVERT3# - Active low interrupt for the External Diode 3 channel (default) GPI5 - General Purpose Input
5
OVERT3#/ GPIO5/ PWM4
GPO5 - General Purpose push/ pull Output GPO5 - General Purpose open drain Output. PWM4 - Open Drain PWM driver PWM4 - Push-Pull PWM driver
6
ALERT#
Active low interrupt - requires external pull-up resistor. CLK_IN - 32.768KHz clock input. GPI1 - General Purpose Input (default)
7
CLK_IN / GPIO1
GPO1 - General Purpose push/ pull Output GPO1 - General Purpose open drain Output. OVERT2# - Active low Interrupt for the External Diode 2 channel (default) GPI4 - General Purpose Input
OD (5V) DI (5V) DO OD (5V) OD (5V) DO
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OVERT2# / GPIO4 / PWM3
GPO4 - General Purpose push/ pull Output GPO4 - General Purpose open drain Output. PWM3 - Open Drain PWM driver PWM3 - Push-Pull PWM driver
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Table 2.1 Pin Description for EMC2106 (continued) PIN NUMBER EMC2106 9 10 11
PIN NAME SYS_SHDN# SMDATA SMCLK
PIN FUNCTION Active low Critical System Shutdown output SMBus data input/output - requires external pull-up resistor SMBus clock input - requires external pull-up resistor GPI6 - General Purpose Input (default)
PIN TYPE OD (5V) DIOD (5V) DIOD (5V) DI (5V) OD (5V) DO OD (5V) DO DI (5V) DO OD (5V) DI (5V) DI (5V) DO OD (5V) DI (5V) OD (5V)
12
GPIO6
GPO6 - General Purpose push/ pull Output GPO6 - General Purpose open drain Output.) PWM2 - Open Drain PWM drive output for Fan 2 (default) PWM2 - Push-Pull PWM drive output for Fan 2
13
PWM2 / GPIO3
GPI3 - General Purpose Input GPO3 - General Purpose push-pull Output GPO3 - General Purpose open drain Output TACH2 - Tachometer input for Fan 2 (default) GPI2 - General Purpose Input
14
TACH2 / GPIO2
GPO2 - General Purpose push-pull Output GPO2 - General Purpose open drain Output
15
TACH1
Tachometer input for Fan 1 OVERT1# - Active low interrupt for the External Diode 1 channel (default)
16
OVERT1# / PWM1
PWM1 - Open Drain PWM drive output for Fan 1 PWM1 - Push-Pull PWM drive output for Fan 1
OD (5V) DO Power Power Power Power
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FAN_OUT FAN_OUT VDD_5V VDD_5V
High Side Fan Driver Output High Side Fan Driver Output Supply for High Side Fan Driver Supply for High Side Fan Driver
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Table 2.1 Pin Description for EMC2106 (continued) PIN NUMBER EMC2106
PIN NAME
PIN FUNCTION TRIP_SET - Determines HW Shutdown temperature features for the hardware shutdown channel VIN4 - General voltage input when Thermal / Critical shutdown disabled
PIN TYPE
AI (2V)
21
TRIP_SET / VIN4
AI (2V) AIO AO (2V)
22 23
SHDN_SEL DAC2
Determines HW Shutdown temperature features and measurement channel Linear Fan Driver Output DN3 / DP4 - Negative (cathode) analog input for External Diode 3 and positive (anode) Analog Input for External Diode 4 (default) VIN3 - General voltage input for use with a thermistor DP3 / DN4 - Positive (anode) analog input for External Diode 3 and negative (cathode) analog input for External Diode 4 (default) VREF_T3 - Reference output for use with a thermistor and to drive VIN3
AIO (2V)
24
DN3 / DP4 / VIN3
AI (2V)
AIO (2V)
25
DP3 / DN4 / VREF
AO (2V) DIT AIO (2V) AI (2V) AIO (2V) AO (2V) Power
26
ADDR_SEL
Selects SMBus slave address DN2 - Negative (cathode) analog input for External Diode 2 (default)
27
DN2 / VIN2 VIN2 - General voltage input for use with a thermistor DP2 - Positive (anode) analog input for External Diode 2 (default)
28
DP2 / VREF_T2 VREF_T2 - Reference output for use with a thermistor and to drive VIN2
Thermal Slug
GND
Ground
The pin type are described in detail below. All pins labelled with (5V) are 5V tolerant. All pin labelled with (2V) should not be exposed to any voltage level greater than 2V.
Table 2.2 Pin Types PIN TYPE Power DI AI DESCRIPTION This pin is used to supply power or ground to the device. Digital Input - this pin is used as a digital input. This pin is 5V tolerant. Analog Input - this pin is used as an input for analog signals.
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Table 2.2 Pin Types (continued) PIN TYPE AO AIO DO DESCRIPTION Analog Output - this pin is used as an output for analog signals. Analog Input / Output - this pin is used as an I/O for analog signals. Push / Pull Digital Output - this pin is used as a digital output. It can both source and sink current. Digital Input / Open Drain Output this pin is used as an digital I/O. When it is used as an output, It is open drain and requires a pull-up resistor. This pin is 5V tolerant. Open Drain Digital Output - this pin is used as a digital output. It is open drain and requires a pull-up resistor. This pin is 5V tolerant.
DIOD
OD
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Chapter 3 Electrical Specifications
Table 3.1 Absolute Maximum Ratings Voltage on 5V tolerant pins including VDD_5V Voltage on VDD pin Voltage on 2V tolerant pins Voltage on any other pin to GND Package Power Dissipation See Note 3.1 Junction to Ambient (JA) See Note 3.2 Operating Ambient Temperature Range Storage Temperature Range ESD Rating, All Pins, HBM -0.3 to 6.5 -0.3 to 4 -0.3 to 2.5 -0.3 to VDD + 0.3 1 up to TA = 85C 40 -40 to 125 -55 to 150 2000 V V V V W C/W C C V
Note: Stresses above those listed could cause permanent damage to the device. This is a stress rating only and functional operation of the device at any other condition above those indicated in the operation sections of this specification is not implied. When powering this device from laboratory or system power supplies, it is important that the Absolute Maximum Ratings not be exceeded or device failure can result. Some power supplies exhibit voltage spikes on their outputs when the AC power is switched on or off. In addition, voltage transients on the AC power line may appear on the DC output. If this possibility exists, it is suggested that a clamp circuit be used. Note 3.1 Note 3.2 Note 3.3 All voltages are relative to ground. The Package Power Dissipation specification assumes a recommended thermal via design consisting of four 12mil vias connected to the ground plane with a 2x2mm thermal landing. Junction to Ambient (JA) is dependent on the design of the thermal vias. Without thermal vias and a thermal landing, the JA is approximately 52C/W including localized PCB temperature increase.
3.1
Electrical Specifications
Table 3.2 Electrical Specifications
VDD = 3V to 3.6V, VDD_5V = 4.5V to 5.5V, TA = -40C to 85C, all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC SYMBOL MIN TYP DC Power Supply Voltage Supply Current (active) VDD IDD 3 3.3 2 3.6 3 V mA 4 Conversions / second Dynamic Averaging Enabled Fan Drivers enabled at max PWM frequency MAX UNIT CONDITIONS
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Table 3.2 Electrical Specifications (continued) VDD = 3V to 3.6V, VDD_5V = 4.5V to 5.5V, TA = -40C to 85C, all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC Supply Current SYMBOL IDD MIN TYP 500 MAX 750 UNIT uA CONDITIONS 1 Conversions / secondDynamic Averaging disabled, Fan Drivers disabled. Fan Driver enabled, No load current
Supply Current from VDD_5V
IDD_5
100 External Temperature Monitors
uA
Temperature Accuracy
0.25 0.5
1 2
C C C
60C < TDIODE < 110C 30C < TDIE < 85C 0C < TDIODE < 125C, 0C < TDIE < 115C
Temperature Resolution Diode decoupling capacitor Resistance Error Corrected CFILTER RSERIES
0.125 2200 2700 100 Internal Temperature Monitor
pF Ohm
Connected across external diode, CPU, GPU, or AMD diode Sum of series resistance in both DP and DN lines
Temperature Accuracy Temperature Resolution
TDIE
1 0.125
2
C C
Note 3.4
Voltage Measurement Total Unadjusted Error Reference Voltage Reference Accuracy TUE VREF 800 1 PWM Fan Driver PWM Resolution PWM Duty Cycle PWM DUTY 0 256 100 High Side Fan Driver Output High Voltage from 5V supply Voltage Accuracy Fan Drive Current Overcurrent Limit VOH_5V VDD_5V - 0.35 VDD_5 V - 0.3 1 2 600 2800 V % mA mA Momentary Current drive at startup for < 2 seconds 1.5V < FAN_OUT < 3.5V ISOURCE = 600mA, VDD_5V = 5V Measured at 3/4 full scale Direct Setting Mode Steps % 1 % mV % Measured at 3/4 full scale
VREF
VFAN_OUT
ISOURCE IOVER
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Table 3.2 Electrical Specifications (continued) VDD = 3V to 3.6V, VDD_5V = 4.5V to 5.5V, TA = -40C to 85C, all Typical values at TA = 27C unless otherwise noted. CHARACTERISTIC DC Short Circuit Current Limit Short circuit delay Output Capacitive Load SYMBOL ISHORT MIN TYP 700 MAX UNIT mA CONDITIONS Sourcing current, Thermal shutdown not triggered, FAN_OUT = 0V
tDFS CLOAD
2 100 Linear DAC Fan Driver
s uF ZESR < 100m at 10kHz
DAC Output High Voltage DAC Output Low Voltage Output Voltage Accuracy Fan Drive Current
VDAC2_OH VDAC2_OL
VDD 0.2 0.3 2 -1 1
V V % mA
IDAC2 = 1mA current source IDAC2 = -1mA current sink Measured at 3/4 full scale Direct Setting Mode
VDAC2
IDAC2
RPM Based Fan Controller Tachometer Range Tachometer Setting Accuracy TACH 480 1 2.5 16000 2 5 RPM % % External oscillator 32.768kHz Internal Oscillator 40C < TDIE < 100C
TACH TACH
Thermal Shutdown Thermal Shutdown Threshold Thermal Shutdown Hysteresis TSDTH TSDHYST 150 50 Digital I/O pins Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Leakage current VIH VIL VOH VOL ILEAK VDD 0.4 0.4 5 2.0 0.8 V V V V uA 4 mA current drive 4 mA current sink ALERT and SYS_SHDN pins Powered and unpowered C C
Note 3.4
TDIE refers to the internal die temperature and may not match TA due to self heating of the device. The internal temperature sensor will return TDIE.
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3.2
SMBus Electrical Specifications (client mode)
Table 3.3 SMBus Electrical Specifications VDD= 3V to 3.6V, TA = -40C to 85C Typical values are at TA = 27C unless otherwise noted.
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
SMBus Interface Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Input High/Low Current Input Capacitance VIH VIL VOH VOL IIH / IIL CIN 5 SMBus Timing Clock Frequency Spike Suppression Bus free time Start to Stop Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Capacitive Load fSMB tSP tBUF tSU:STA tSU:STP tHD:DAT tSU:DAT tLOW tHIGH tFALL tRISE CLOAD 1.3 0.6 0.6 0.6 0.6 1.3 0.6 300 300 400 6 72 10 400 50 kHz ns us us us us us us us ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns per bus line VDD - 0.4 0.4 5 2.0 0.8 V V V V uA pF 4 mA current sink Powered and unpowered
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3.3
EEPROM Loader Electrical Specifications
Table 3.4 EEPROM Loader Electrical Specifications VDD = 3.0V to 3.6V, TA = -40oC - 85oC, Typical values are at TA = 27C unless otherwise noted
CHARACTERISTIC
SYMBOL
MIN
TYP
MAX
UNITS
CONDITIONS
Interface Input High/Low Current Hysteresis Input Capacitance Output Low Sink Current CIN 4 Timing Loading Delay Loading Time Clock Frequency Spike Suppression Bus free time Start to Stop Hold Time: Start Setup Time: Start Setup Time: Stop Data Hold Time Data Setup Time Clock Low Period Clock High Period Clock/Data Fall time Clock/Data Rise time Capacitive Load tDLY tLOAD fSMB tSP tBUF tHD:STA tSU:STA tSU:STO tHD:DAT tSU:DAT tLOW tHIGH tFALL tRISE CLOAD 1.3 0.6 0.6 0.6 0.3 100 1.3 0.6 300 300 400 10 50 50 50 ms ms kHz ns us us us us us ns us us ns ns pF Min = 20+0.1CLOAD ns Min = 20+0.1CLOAD ns per bus line Delay after power-up until EEPROM loading begins. (See Section 4.9.) IIH / IIL -1 420 5 1 uA mV pF mA VOL = 0.4V
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Chapter 4 Communications
4.1 System Management Bus Interface Protocol
The EMC2106 communicates with a host controller, such as an SMSC SIO, through the SMBus. The SMBus is a two-wire serial communication protocol between a computer host and its peripheral devices. A detailed timing diagram is shown in Figure 4.1. Stretching of the SMCLK signal is supported, however the EMC2106 will not stretch the clock signal. The EMC2106 powers up as an SMBus client(after loading from EEPROM as applicable).
TLOW
THIGH
THD:STA TSU:STO
SMCLK
THD:STA
TRISE
TFALL
THD:DAT
TSU:DAT
TSU:STA
SMDATA
TBUF
P
S
S - Start Condition
S
P - Stop Condition P
Figure 4.1 SMBus Timing Diagram The EMC2106 contains a single SMBus interface. The SMBus address is determined by the ADDR_SEL pin (see Section 4.7)The EMC2106 client interfaces are SMBus 2.0 compatible and support Send Byte, Read Byte, Receive Byte and the Alert Response Address as valid protocols. These protocols are used as shown below. All of the below protocols use the convention in Table 4.1.
Table 4.1 Protocol Format DATA SENT TO DEVICE # of bits sent DATA SENT TO THE HOST # of bits sent
4.2
Write Byte
The Write Byte is used to write one byte of data to the registers as shown below Table 4.2:
Table 4.2 Write Byte Protocol SLAVE ADDRESS 0101_111 REGISTER ADDRESS XXh REGISTER DATA XXh
START 0 -> 1
WR 0
ACK 0
ACK 0
ACK 0
STOP 1 -> 0
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4.3
Read Byte
The Read Byte protocol is used to read one byte of data from the registers as shown in Table 4.3.
Table 4.3 Read Byte Protocol
START SLAVE ADDRESS 0101_111 WR ACK Register Address XXh ACK START Slave Address 0101_111 RD ACK Register Data XXh NACK STOP
0 -> 1
0
0
0
0 -> 1
1
0
1
1 -> 0
4.4
Send Byte
The Send Byte protocol is used to set the internal address register pointer to the correct address location. No data is transferred during the Send Byte protocol as shown in Table 4.4.
Table 4.4 Send Byte Protocol SLAVE ADDRESS 0101_111 REGISTER ADDRESS XXh
START 0 -> 1
WR 0
ACK 0
ACK 0
STOP 1 -> 0
4.5
Receive Byte
The Receive Byte protocol is used to read data from a register when the internal register address pointer is known to be at the right location (e.g. set via Send Byte). This is used for consecutive reads of the same register as shown in Table 4.5.
Table 4.5 Receive Byte Protocol SLAVE ADDRESS 0101_111
START 0 -> 1
RD 1
ACK 0
REGISTER DATA XXh
NACK 1
STOP 1 -> 0
4.6
Alert Response Address
The ALERT# output can be used as a processor interrupt or as an SMBus Alert when configured to operate as an interrupt. When it detects that the ALERT# pin is asserted, the host will send the Alert Response Address (ARA) to the general address of 0001_100xb. All devices with active interrupts will respond with their client address as shown in Table 4.6. Table 4.6 Alert Response Address Protocol ALERT RESPONSE ADDRESS 0001_100
START 0 -> 1
RD 1
ACK 0
DEVICE ADDRESS 0101_111
NACK 1
STOP 1 -> 0
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The EMC2106 will respond to the ARA in the following way if the ALERT# pin is asserted. 1. Send Slave Address and verify that full slave address was sent (i.e. the SMBus communication from the device was not prematurely stopped due to a bus contention event). 2. Set the MASK bit to clear the ALERT# pin. 3. The ARA will NOT affect the OVERT1#, OVERT2#, and OVERT3# pins. These pins will be asserted as long as the error condition is present. When the error condition is removed, the pins will be cleared.
4.7
SMBus Address
The EMC2106 SMBus Address is determined by the status of the ADDR_SEL pin as shown in Table 4.7.
Table 4.7 ADDR_SEL Pin Decode ADDR_SEL `0' (GND) `Z' (open) `1' (VDD) SMBUS ADDRESS 0101_111xb 0101_111xb 0101_110xb SMBus Client EEPROM Programming SMBus Client FUNCTION
Attempting to communicate with the EMC2106 SMBus interface with an invalid slave address or invalid protocol will result in no response from the device and will not affect its register contents.
4.8
SMBus Time-out
The EMC2106 includes an SMBus time-out feature. Following a 30ms period of inactivity on the SMBus, the device will time-out and reset the SMBus interface.
4.9
Programming from EEPROM
When configured to load from EEPROM (see Section 4.7), the EMC2106 acts as a simple SMBus Master to read data from a connected EEPROM using the following procedure. 1. After power-up the EMC2106 waits for 10ms with the SMDATA and SMCLK pins tri-stated. 2. Once the wait period has elapsed, the EMC2106 sends a START signal followed by the 7 bit client address 1010 _000xb followed by a `0b' and waits for an ACK signal from the EEPROM. 3. When the EEPROM sends the ACK signal, the EMC2106 will send a second start signal and continue sending the Block Read Command (see Table 4.8) to the same slave address. It reads 256 data bytes from the EEPROM sending an ACK between each data byte. When 256 data bytes have been received, it sends a NACK signal followed by a STOP bit. 4. Resets the device as an SMBus Client with slave address 0101_111xb. If the EMC2106 does not receive an acknowledge bit from the EEPROM then the following will occur: 1. The ALERT# pin will be asserted and will remain asserted until a Host device initiates communication with the EMC2106 and reads the Status Register. The ALERT# pin will be deasserted after a single Status Register read. 2. The EMC2106 will reset its SMBus protocol as a slave interface and start operating from the default conditions with slave address 0101_111xb.
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Table 4.8 Block Read Byte Protocol
START SLAVE ADDRESS 0101_111 WR ACK Register Address 00h ACK START SLAVE ADDRESS 0101_111 RD ACK Register Data (00h) XXh ...
0-> 1
0
0
0
0 -> 1
1
0
ACK
Register Data (01h) XXh
ACK
Register Data (02h) XXh
ACK
Register Data (03h) XXh
...
ACK
Register Data (FFh) XXh
NACK
STOP
0
0
0
...
0
1
1 -> 0
Note: The shaded columns represent data sent from the EMC2106 to the EEPROM device. APPLICATION NOTE: It is recommended that the EEPROM that is used be an AT24C02B or equivalent device. The EEPROM slave address must be 1010_000xb. The device must support a block-read command, 8-bit addressing, and 8-bit data formatting using a 2-wire bus. The device must support 3.3V digital switching logic and may not pull the SMCLK and SMDATA pins above 5V. Data must be transmitted MSB first. APPLICATION NOTE: No other SMBus Master should exist on the SMDATA and SMCLK lines. The presence of another SMBus Master will cause errors in reading from the EEPROM. The EEPROM should be loaded to mirror the register set of the EMC2106 with the desired configuration set. All undefined registers in the EMC2106 register set should be loaded with 00h in the EEPROM. Likewise, all registers that are read-only in the EMC2106 register set should be loaded with 00h in the EEPROM. Because of the interaction between the Fan Control Look-up Tables and the Fan Configuration Register, the EEPROM Loader stores the contents of the Fan Configuration Registers and updates these registers at the end of the EEPROM loading cycle.
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Chapter 5 Product Description
The EMC2106 is an SMBus compliant fan controller with up to four (up to 4 external) temperature channels. It contains two fan drivers, a High Side fan driver capable of sourcing 600mA from a 5V supply and a linear DAC fan driver. In addition, the EMC2106 contains up to four (4) PWM outputs (two of which can be used with the RPM based Fan Speed Control Algorithm). The fan drivers can be operated using two methods each with two modes. The methods include an RPM based Fan Speed Control Algorithm and a direct fan drive setting. The modes include manually programming the desired settings or using the internal programmable temperature look-up table to select the desired setting based on measured temperature. The temperature monitors offer 1C accuracy (for external diodes) with sophisticated features to reduce errors introduced by series resistance and beta variation of substrate thermal diode transistors commonly found in processors (including support for BJT or transistor model for CPU diodes). The EMC2106 also includes a hardware programmable temperature limit and dedicated system shutdown output for thermal protection of critical circuitry. Any of the three temperature channels can be configured to measure a thermistor or voltage channel using a precision reference voltage for reduced system complexity. Figure 5.1 shows a system diagram of the EMC2106.
3.3V 3.3V 5V
VDD SMCLK
VDD_5V (2) FAN_OUT (2)
KBC
SMDATA ALERT#
3.3V
CPU Thermal diode
ADDR_SEL TACH1 DP1* DN1* OVERT1#* OVERT2#* 0.8V
tachometer
EMC2106
3.3V
GPU Thermal diode
DP2* DN2* 1.2k
TACH2* DAC2* CLK_IN*
tachometer
Drive Circuit 32.768KHz Clock APD (optional)
3.3V
TRIP_SET*
GPIO6 GPIO3* DP3 / DN4*
SYS_SHDN# SHDN_SEL
DN3 / DN4* OVERT3#* GND
* denotes other functions available on this pin
Figure 5.1 System Diagram of EMC2106
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5.1
Critical/Thermal Shutdown
The EMC2106 provides a hardware Critical/Thermal Shutdown function for systems. Figure 5.2 is a block diagram of this Critical/Thermal Shutdown function. The Critical/Thermal Shutdown function in the EMC2106 accepts configuration information from the fixed states of the SHDN_SEL pin as described in Section 5.1.1. Each of the software programmed temperature limits can be optionally configured to act as inputs to the Critical / Thermal Shutdown independent of the hardware shutdown operation. When configured to operate this way, the SYS_SHDN# pin will be asserted when the temperature meets or exceeds the limit. The pin will be released when the temperature drops below the limit however the individual status bits will not be cleared if set (see Section 6.13). The analog portion of the Critical/Thermal Shutdown function monitors the hardware determined temperature channel (see Section 5.1.1). This measured temperature is then compared with TRIP_SET point. This TRIP_SET point is set by the system designer with a single external resistor divider as described in Section 5.1.2. The SYS_SHDN# is asserted when the indicated temperature exceeds the temperature threshold established by the TRIP_SET input pin for a number of consecutive measurements defined by the fault queue. If the HW_SHDN output is asserted and the temperature drops below the Thermal / Critical Shutdown threshold then it will be set to a logic `0' state.
Register Enabled Sensor
Critical Shutdown Logic
Configuration Register SMBus Traffic
Register Enabled Sensor
Register Enabled Sensor
Temperature Conversion and Limit Registers
SW_SHDN
Register Enabled Sensor Internal Diode Channel External Diode 1 Temperature Conversion VREF 1 0 TRIP_SET HW_SHDN SYS_SHDN# PIN Decode `1'
SHDN_SEL
Voltage Conversion
Figure 5.2 EMC2106 Critical/Thermal Shutdown Block Diagram
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5.1.1
SHDN_SEL Pin
The EMC2106 has a `strappable' input (SHDN_SEL) allowing for configuration of the hardware Critical/Thermal Shutdown input channels. This pin has 3 possible states and is monitored and decoded by the EMC2106 at power-up. The three possible states are 0 (tied to GND), 1 (tied to 3.3V) or High-Z (open). The state of this pin determines which external diode configuration is used for the Critical / Thermal shutdown function. The different configurations of the SHDN_SEL pin are described in Table 5.1. SHDN_SEL applies only to the selected temperature channel.
Table 5.1 SHDN_SEL Pin Configuration FUNCTION NAME Intel Transistor Mode (substrate PNP) CRITICAL / THERMAL SHUTDOWN RANGE High - 92C to 154C
SHDN_SEL 0
TEMPERATURE MONITORING FEATURES The external diode 1 channel is configured with Beta Compensation enabled and Resistance Error Correction enabled. This mode is ideal for monitoring a substrate transistor such as an Intel CPU thermal diode. The external diode 1 channel is configured with Beta Compensation disabled and Resistance Error Correction disabled. This mode is ideal for monitoring an AMD processor diode or a 2N3904 diode. The internal diode is linked to the Hardware set Thermal / Critical shutdown circuitry and the SYS_SHDN# pin.
High-Z (open)
AMD CPU / Diode Mode
Low - 60C to 122C
1
Internal
Low - 60C to 122C
5.1.2
TRIP_SET / VIN4 Pin
The EMC2106's TRIP_SET / VIN4 pin is an analog input to the Critical/Thermal Shutdown block which sets the Thermal Shutdown temperature. The system designer creates a voltage level at the input through a simple resistor connected to GND as shown in Figure 5.1. The value of this resistor is used to create an input voltage on the TRIP_SET / VIN4 pin which is translated into a temperature ranging from 60C to 122C or 90C to 152C as enumerated in Table 5.2. When the SHDN_SEL pin is pulled to `1' at power up, then the TRIP_SET / VIN4 pin is configured to measure VIN4 as its primary function. The circuitry will still calculate the thermal / critical shutdown threshold based on the voltage and compare this temperature against the Internal Diode temperature. This will cause the SYS_SHDN# pin to assert if the measured temperature exceeds this threshold. The device will also compare the measured voltage against the VIN4 High and Low limits. This function is not available if SHDN_SEL is set to `0' or `High-Z' at power up.
APPLICATION NOTE: If the SHDN_SEL pin is pulled to `1' at power up and the TRIP_SET / VIN4 pin is intended for use as a voltage input then the SYS_SHDN# pin should be ignored. APPLICATION NOTE: If the SHDN_SEL pin is pulled to `1' at power up and the TRIP_SET / VIN4 pin is intended to be used to set a threshold level then the VIN4 channel should be masked. Furthermore, the voltage on the pin must be externally generated based on Equation [1]. Do not use Table 5.2. APPLICATION NOTE: When used in its TRIP_SET mode (i.e. the SHDN_SEL pin is not set to a logic `1'), current only flows when the TRIP_SET / VIN4 pin is being monitored. At all other times, the internal reference voltage is removed and the TRIP_SET / VIN4 pin will be pulled down to ground.
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APPLICATION NOTE: The TRIP_SET / VIN4 pin circuitry is designed to use a 1% resistor externally. Using a 1% resistor will result in the Thermal / Critical Shutdown temperature being decoded correctly. If a 5% resistor is used, then the Thermal / Critical Shutdown temperature may be decoded with as much as 1C error.
T TRIP - T MIN V TRIP = ---------------------------------80
VTRIP is the TRIP_SET voltage TMIN is the minimum temperature based on the range [1]
Table 5.2 TRIP_SET Resistor Setting TTRIP (C) LOW RANGE 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 TTRIP (C) HIGH RANGE 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 TTRIP (C) LOW RANGE 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 TTRIP (C) HIGH RANGE 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146
RSET (1%) 0.0 28.7 48.7 69.8 90.9 113 137 158 182 210 237 261 294 324 348 383 412 453 487 523 562 604 649
RSET (1%) 1240 1330 1400 1500 1580 1690 1820 1960 2050 2210 2370 2550 2740 2940 3160 3480 3740 4120 4530 4990 5490 6040 6810
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Table 5.2 TRIP_SET Resistor Setting (continued) TTRIP (C) LOW RANGE 83 84 85 86 87 88 89 90 91 TTRIP (C) HIGH RANGE 115 116 117 118 119 120 121 122 123 TTRIP (C) LOW RANGE 115 116 117 118 119 120 121 122 60 TTRIP (C) HIGH RANGE 147 148 149 150 151 152 153 154 92
RSET (1%) 698 750 787 845 909 953 1020 1100 1150
RSET (1%) 7870 9090 10700 12700 15800 20500 29400 49900 Open
5.2
Fan Control Modes of Operation
The EMC2106 has four modes of operation for each fan driver. Each mode of operation uses the Ramp Rate control and Spin Up Routine. 1. Direct Setting Mode- in this mode of operation, the user directly controls the fan drive setting. Updating the Fan Driver Setting Register (see Section 6.23) will instantly update the fan drive. Ramp Rate control is optional and enabled via the EN_RRC bits. This is the default mode. The Direct Setting Mode is enabled by clearing the LUT_LOCK bit in the Look Up Table Configuration Register (see Section 6.35) while the TACH / DRIVE bit is set to `0'. Whenever the Direct Setting Mode is enabled the current drive will be changed to what was last written into the Fan Driver Setting Register. 2. Fan Speed Control Mode (FSC) - in this mode of operation, the user determines a target tachometer count and the drive setting is automatically updated to achieve this target speed. The algorithm uses the Spin Up Routine and has user definable ramp rate controls. This mode is enabled by clearing the LUT_LOCK bit in the Look Up Table (LUT) Configuration Register and setting the EN_ALGO bit in the Fan Configuration Register. 3. Using the Look Up Table with Fan Drive Settings (Direct Setting w/ LUT Mode) - In this mode of operation, the user programs the Look Up Table with fan drive settings and corresponding temperature thresholds. The fan drive is set based on the measured temperatures and the corresponding drive settings. Ramp Rate control is optional and enabled via the EN_RRC bits. This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit while the TACH / DRIVE bit is set to `1'. The TACH / DRIVE bit in the Look Up Table Configuration Register MUST be set to `1' or the fan drive settings will be incorrectly set. Setting this bit to `1' ensures the settings will be PWM settings. 4. Using the Look Up Table with RPM Target Settings (FSC w/ LUT Mode) - In this mode of operation, the user programs the Look Up Table with TACH Target values and corresponding temperature thresholds. The TACH Target will be set based on the measured temperatures and the corresponding target settings. The fan drive settings will be determined automatically based on the RPM based Fan Speed Control Algorithm This mode is enabled by programming the Look Up Table then setting the LUT_LOCK bit while the TACH / DRIVE bit is set to `0'
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The TACH / DRIVE bit in the Look Up Table Configuration Register MUST be set to `0' or the TACH Target values will be incorrectly set. Setting this bit to `0' ensures tha the settings will be RPM settings (Tachometer counts). APPLICATION NOTE: It is important that the TACH Target settings are in the proper format when using the RPM based Fan Speed Control Algorithm.
Table 5.3 Fan Controls Active for Operating Mode DIRECT SETTING MODE Fan Driver Setting (read / write) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Valid TACH Count TACH Reading DIRECT SETTING W/ LUT MODE Fan Driver Setting (read only) EDGES[1:0] UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step
FSC MODE Fan Driver Setting (read only) EDGES[1:0] (Fan Configuration) RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Fan Minimum Drive Valid TACH Count TACH Target (read / write) TACH Reading -
FSC W/ LUT MODE Fan Driver Setting (read only) EDGES[1:0] RANGE[1:0] (Fan Configuration) UPDATE[2:0] (Fan Configuration) LEVEL (Spin Up Configuration) SPINUP_TIME[1:0] (Spin Up Configuration) Fan Step Fan Minimum Drive
Valid TACH Count TACH Reading Look Up Table Drive / Temperature Settings (read only) -
Valid TACH Count TACH Target (read only) TACH Reading Look up Table Drive / Temperature Settings (read only) DRIVE_FAIL_CNT[1:0] and Drive Band Fail Registers
-
DRIVE_FAIL_CNT[1:0] and Drive Band Fail Registers
5.3
High Side Fan Driver
The EMC2106's contains a 5V, 600mA, linear high side fan driver to directly drive a 5V fan. By fully integrating the linear fan driver, the typical requirement for the discrete pass device and other external linearization circuitry is completely eliminated. The linear fan driver is driven by an 8-bit DAC providing better than 20mV resolution between steps.
5.3.1
Over Current Limit
The High Side Fan Driver contains circuitry to allow for significant over current levels to accommodate transient conditions on the FAN pins. The over current limit is dependent upon the output voltage with the limit dropping as the voltage nears 0V.
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If the fan driver current detects a short-circuit condition for longer than 2 seconds, then the I_SHORT status bit is set and an interrupt generated. Additionally, the High Side Fan Driver will be disabled for 8 seconds. After this 8 second time has elapsed, it will be allowed to restart invoking the Spin Up Routine before returning to its previous drive setting. APPLICATION NOTE: If the FSC Algorithm is active, then it will generate errant SPIN_FAIL interrupts during the 8 second time that the fan driver is held off.
5.4
Linear DAC Fan Driver
The EMC2106 contains an internal linear DAC for use as a fan driver. This DAC output voltage has 8-bit resolution from 0V to 3.3V. The linear DAC fan driver is also capable of sourcing and sinking up to 1 mA of current. The Linear DAC Fan Driver is biased from the VDD_5V supply and this voltage must be present for the DAC driver to operate properly.
5.5
PWM Fan Driver
The EMC2106 supports up to four (4) PWM output drivers. Each output driver can be configured to operate as an open-drain (default) or push-pull driver and each driver can be configured with normal or inverse polarity. Additionally, the PWM frequencies for PWM1, PWM2, and the two optional PWM drivers PWM3 and PWM4 are independently programmable with ranges from 9.5Hz to 26kHz in four programmable frequency bands.
5.6
Fan Control Look-Up Table
The EMC2106 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to each fan driver. In this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. The user programs the look-up table based on the desired operation. If the RPM based Fan Speed Control Algorithm is to be used (see Section 5.7), then the user must program an RPM target for each temperature setting of interest. Alternately, if the RPM based Fan Speed Control Algorithm is not to be used, then the user must program a drive setting for each temperature setting of interest. If the measured temperature on the External Diode channel meets or exceeds any of the temperature thresholds for any of the temperature columns (see Appendix B), the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. When the measured temperature drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to the corresponding lower set point. Figure 5.3 shows an example of this operation using temperature - drive setting pairs for a single channel. See Appendix B for examples of the Look Up Table operation.
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Fan Setting Temp T8 T8 - Hyst T7 T7 - Hyst T6 T6 - Hyst T5 T5 - Hyst T4 T4 - Hyst S8 S7 S6
S5
S4 Averaged Temperature S3 Fan Setting S2
T3 T3 - Hyst
T2 T2 - Hyst T1
Measurement taken
S1
Time
Figure 5.3 Fan Control Look-Up Table Example
5.6.1
Programming the Look Up Table
When the Look Up Table is used, it must be loaded and configured correctly based on the system requirements. The following steps outline the procedure. 1. Determine whether the Look Up Table will drive a fan setting or a tachometer target value and set the TACH / DRIVE bit in the Fan LUT Configuration Register. 2. Determine which measurement channels (up to four) are to be used with the Look Up Table and set the TEMP3_CFG and TEMP4_CFG bits accordingly in the Fan LUT Configuration Register. 3. For each step to be used in the LUT, set the Fan Setting (either fan setting or TACH Target as set by the TACH / DRIVE bit). If a setting is not used, then set it to FFh (if a fan setting) or 00h (if a TACH Target). Load the lowest settings first in ascending order (i.e. Fan Setting 1 is the lowest setting greater than "off". Fan Setting 2 is the next highest setting, etc.). 4. For each step to be used in the LUT, set each of the measurement channel thresholds. These values must be set in the same data format that the data is presented. If DTS is to be used, then
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the format should be in temperature with a maximum threshold of 100C (64h). If a measurement channel is not used, then set the threshold at FFh. 5. Set the Hysteresis value to be smaller than the smallest threshold step. 6. Configure the RPM based Fan Speed Control Algorithm if it is to be used. 7. Set the LUT_LOCK bit to enable the Look Up Table and begin fan control.
5.6.2
DTS Support
The EMC2106 supports DTS (Intel's Digital Temperature Sensor) data in the Fan Control Look Up Table. Intel's DTS data is a positive number that represents the processor's relative temperature below a fixed value called TCONTROL which is generally equal to 100C for Intel Mobile processors. For example, a DTS value of 10C means that the actual processor temperature is 10C below TCONTROL or equal to 90C. Either or both of the Pushed Temperature Registers can be written with DTS data and used to control the respective fan driver. When DTS data is entered, then the USE_DTS_Fx bit must be set in the Fan LUT Configuration register. Once this bit is set, the DTS data entered is automatically subtracted from a value of 100C. This delta value is then used in the Look Up Table as standard temperature data. See Appendix B for examples on using DTS data in the Look Up Table.
APPLICATION NOTE: The device is designed with the assumption that TCONTROL is 100C. As such, all DTS related conversions are done based on this value including Look Up Table comparisons. If TCONTROL is adjusted (i.e. TCONTROL is shifted to 105C), then all of the Look Up Table thresholds should be adjusted by a value equal to TCONTROL - 100C.
5.7
RPM based Fan Speed Control Algorithm (FSC)
The EMC2106 includes two RPM based Fan Speed Control Algorithms. Each algorithm operates independently and controls a separate fan driver. Each algorithm can be controlled manually (by setting the target fan speed) or via a look up table. This fan control algorithm uses Proportional, Integral, and Derivative terms to automatically approach and maintain the system's desired fan speed to an accuracy directly proportional to the accuracy of the clock source. Figure 5.4 shows a simple flow diagram of the RPM based Fan Speed Control Algorithm operation. The desired tachometer count is set by the user inputting the desired number of 32.768KHz cycles that occur per fan revolution. This is done by either manually setting the TACH Target Register or by programming the Temperature Look-Up Table. The user may change the target count at any time. The user may also set the target count to FFh in order to disable the fan driver for lower current operation. For example, if a desired RPM rate for a 2-pole fan is 3000 RPMs, then the user would input the hexidecimal equivalent of 1296 (51h in the TACH Target Register). This number represents the number of 32.768KHz cycles that would occur during the time it takes the fan to complete a single revolution when it is spinning at 3000RPMs. The EMC2106's RPM based Fan Speed Control Algorithm has programmable configuration settings for parameters such as ramp-rate control and spin up conditions. The fan driver automatically detects and attempts to alleviate a stalled/stuck fan condition while also asserting the ALERT# pin. The EMC2106 works with fans that operate up to 16,000 RPMs and provide a valid tachometer signal. The fan controller will function either with an externally supplied 32.768KHz clock source or with it's own internal 32kHz oscillator depending on the required accuracy.
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Set TACH Target Count
Measure Fan Speed
Spin Up Required ? No
Yes
Perform Spin Up Routine
Yes Maintain Fan Drive
TACH Reading = TACH Target?
No
Yes
TACH Reading < TACH Target?
No
Ramp Rate Control
Reduce Fan Drive
Increase Fan Drive
Figure 5.4 RPM based Fan Speed Control Algorithm
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5.7.1
Programming the RPM Based Fan Speed Control Algorithm
The RPM based Fan Speed Control Algorithm is disabled upon device power up. The following registers control the algorithm. The EMC2106 fan control registers are pre-loaded with defaults that will work for a wide variety of fans so only the TACH Target Register is required to set a fan speed. The other fan control registers can be used to fine-tune the algorithm behavior based on application requirements. Note that steps 1 - 6 are optional and need only be performed if the default settings do not provide the desired fan response. 1. Set the Spin Up Configuration Register to the Spin Up Level and Spin Time desired. 2. Set the Fan Step Register to the desired step size. 3. Set the Fan Minimum Drive Register to the minimum drive value that will maintain fan operation. 4. Set the Update Time, and Edges options in the Fan Configuration Register. 5. Set the Valid TACH Count Register to the highest tach count that indicates the fan is spinning. 6. Set the TACH Target Register to the desired tachometer count. 7. Enable the RPM based Fan Speed Control Algorithm by setting the EN_ALGO bit.
5.8
Tachometer Measurement
The tachometer measurement circuitry is used in conjunction with the RPM based Fan Speed Control Algorithm to update the fan driver output. Additionally, it can be used in Direct Setting mode as a diagnostic for host based fan control. This method monitors the TACHx signal in real time. It constantly updates the tachometer measurement by reporting the number of clocks between a user programmed number of edges on the TACHx signal (see Table 6.33) The tachometer measurement provides fast response times for the RPM based Fan Speed Control Algorithm and the data is presented as a count value that represents the fan RPM period. When this method is used, all fan target values must be input as a count value for proper operation.
APPLICATION NOTE: The tachometer measurement method works independently of the drive settings. If the device is put into Direct Setting and the fan drive is set at a level that is lower than the fan can operate (including zero drive), then the tachometer measurement may signal a Stalled Fan condition and assert an interrupt.
5.8.1
Stalled Fan
A Stalled fan is detected if the tach counter exceeds the user-programmable Valid TACH Count setting then it will flag the fan as stalled and trigger an interrupt. If the RPM based Fan Speed Control Algorithm is enabled, the algorithm will automatically attempt to restart the fan until it detects a valid tachometer level or is disabled. The FAN_STALL Status bit indicates that a stalled fan was detected. This bit is checked conditionally depending on the mode of operation. Whenever the Direct Setting Mode or Direct Setting with LUT Mode is enabled or whenever the Spin Up Routine is enabled, the FAN_STALL interrupt will be masked for the duration of the programmed Spin Up Time (see Table 6.43) to allow the fan an opportunity to reach a valid speed without generating unnecessary interrupts. In Direct Setting Mode or Direct Setting w/ LUT Mode, and the tachometer measurement is using the Tach Period Measurement method, then whenever the TACH Reading Register value exceeds the Valid TACH Count Register setting, the FAN_STALL status bit will be set.
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When using the RPM based Fan Speed Control Algorithm (either FSC Mode or LUT with FSC Mode), the stalled fan condition is checked whenever the Update Time is met and the fan drive setting is updated. It is not a continuous check.
5.8.2
32kHz Clock Source
The EMC2106 allows the user to choose between supplying an external 32.768kHz clock or use of the internal 32kHz oscillator to measure the tachometer signal. This clock source is used by the RPM based Fan Speed Control Algorithm to calculate the current fan speed. This fan controller accuracy is directly proportional to the accuracy of the clock source. The external clock is provided on the CLK_IN. In order for the external clock to be used, the EXT_CLK bit must be set in the Configuration Register.
5.8.3
Aging Fan or Invalid Drive Detection
This is useful to detect aging fan conditions (where the fan's natural maximum speed degrades over time) or incorrect fan speed settings.The EMC2106 contains circuitry that detects that the programmed fan speed can be reached by the fan. If the target fan speed cannot be reached within a user defined band of tach counts at maximum drive then the DRIVE_FAIL status bits are set and the ALERT# pin is asserted.
5.9
Spin Up Routine
The EMC2106 also contains programmable circuitry to control the spin up behavior of the fan driver to ensure proper fan operation. The Spin Up Routine is initiated in Direct Setting mode (with or without the Look Up Table - when enabled) when the setting value changes from 00h to anything else. When the Fan Speed Control Algorithm is enabled, the Spin Up Routine is initiated under the following conditions when the Tach Period Measurement method of tach measurement is used: 1. The TACH Target Register value changes from a value of FFh to a value that is less than the Valid TACH Count (see Section 6.31). 2. The RPM based Fan Speed Control Algorithm's measured TACH Reading Register value is greater than the Valid TACH Count setting. When the Spin Up Routine is operating, the fan driver is set to full scale (optional) for one quarter of the total user defined spin up time. For the remaining spin up time, the fan driver output is set a a user defined level (30% through 65% drive). After the Spin Up Routine has finished, the EMC2106 measures the TACHx signal. If the measured TACH Reading Register value is higher than the Valid TACH Count Register setting, the FAN_SPIN status bit is set and the Spin Up Routine will automatically attempt to restart the fan. Figure 5.5 shows an example of the Spin Up Routine in response to a programmed fan speed change based on the first condition above.
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100% (optional)
30% through 65% Fan Step
New Target Count Algorithm controlled drive Prev Target Count = FFh 1/4 of Spin Up Time
Update Time Spin Up Time
Target Count Changed
Check TACH
Target Count Reached
Figure 5.5 Spin Up Routine
5.10
Ramp Rate Control
The Fan Driver can be configured with automatic ramp rate control. Ramp rate control is accomplished by adjusting the drive output settings based on the Maximum Fan Step Register settings and the Update Time settings. If the RPM based Fan Speed Control Algorithm is used, then this ramp rate control is automatically used. The user programs a maximum step size for the fan drive setting and an update time. The update time varies from 100ms to 1.6s while the fan drive maximum step can vary from 1 count to 31 counts. When a new fan drive setting is entered, the delta from the next fan drive setting and the previous fan drive setting is determined. If this delta is greater than the Max Step settings, then the fan drive setting is incrementally adjusted every 100ms to 1.6s as determined by the Update Time until the target fan drive setting is reached. See Figure 5.6.
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Next Desired Setting Max Step Max Step
Previous Setting
Update Time
Update Time
Setting Changed
Figure 5.6 Ramp Rate Control
5.11
Watchdog Timer
The EMC2106 contains two internal Watchdog Timers. Once the device has powered up the watchdog timer monitors the SMBus traffic for signs of activity. The Watchdog Timer starts when the internal supply has reached its operating point. The Watchdog Timer only starts immediately after power-up and once it has been triggered or deactivated will not restart. Each fan driver has an independent watchdog timer. Disabling the watchdog associated with Fan 1 will not disable the watchdog associated with Fan 2. If four (4) seconds elapse without the system host programming the device, then the watchdog will be triggered and the following will occur: 1. The WATCH status bit will be set. 2. The fan driver will be set to full scale drive. It will remain at full scale drive until one of the three conditions listed below are met. If the Watchdog Timer is triggered, the following three operations will disable the timer and return the device to normal operation. Alternately, if the Watchdog Timer has not yet been triggered performing any one of the following will disable it. 1. Writing the Fan Setting Register will disable the Watchdog Timer. 2. Enabling the RPM based Fan Speed Control Algorithm by setting the EN_ALGO bit will disable the Watchdog Timer. The fan driver will be set based on the RPM based Fan Speed Control Algorithm. 3. Setting the LUT_LOCK bit will disable the Watchdog Timer. The fan driver will be set based on the Look Up Table settings. Writing any other configuration registers will not disable the Watchdog Timer.
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APPLICATION NOTE: Disabling the Watchdog will not automatically set the fan drive. This must be done manually (or via the Look Up Table).
5.12
Internal Thermal Shutdown (TSD)
The EMC2106 contains an internal thermal shutdown circuit that monitors the internal die temperature. If the die temperature exceeds the Thermal Shutdown Threshold (see Table 3.2), then the following will occur: 1. The High Side Fan Driver is disabled. It will remain disabled until the internal temperature drops below the threshold temperature minus 50C. 2. The TSD Status bit will be set and the SYS_SHDN# pin asserted. 3. The SYS_SHDN# pin is asserted.
APPLICATION NOTE: When the fan driver is disabled via a thermal shutdown event, the drive settings will not be altered. Thus, when the temperature drops below the threshold minus the hysteresis, the fan will return to its previous drive setting.
5.13
Fault Queue
The EMC2106 contains a programmable fault queue on all fault conditions except a FAN_SHORT or TSD condition (including all temperature high, low, and tcrit limits as well as the hardware set thermal limit). The fault queue defines how many consecutive out-of-limit conditions must be reported before the corresponding status bit is set (and the ALERT# pin asserted).
APPLICATION NOTE: With the exception of the Tcrit limit, the fault queue is not applied to the internal diode measurement.
5.14
Temperature Monitoring
The EMC2106 can monitor the temperature of up to four (4) externally connected diodes as well as the internal or ambient temperature. Each channel is configured with the following features enabled or disabled based on user settings and system requirements.
5.14.1
Dynamic Averaging
The EMC2106 supports dynamic averaging. When enabled, this feature changes the conversion time for all channels based on the selected conversion rate. This essentially increases the averaging factor as shown in Table 5.4. The benefits of Dynamic Averaging are improved noise rejection due to the longer integration time as well as less random variation on the temperature measurement.
Table 5.4 Dynamic Averaging Behavior AVERAGING FACTOR (RELATIVE TO 11-BIT CONVERSI0N) DYNAMIC AVERAGING ENABLED 8x 4x 2x 1x DYNAMIC AVERAGING DISABLED 1x 1x 1x 1x
CONVERSION RATE 1 / sec 2 / sec 4 / sec 8 / sec
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5.14.2
Resistance Error Correction
The EMC2106 includes active Resistance Error Correction to remove the effect of up to 100 ohms of series resistance. Without this automatic feature, voltage developed across the parasitic resistance in the remote diode path causes the temperature to read higher than the true temperature is. The error induced by parasitic resistance is approximately +0.7C per ohm. Sources of parasitic resistance include bulk resistance in the remote temperature transistor junctions, series resistance in the CPU, and resistance in the printed circuit board traces and package leads. Resistance error correction in the EMC2106 eliminates the need to characterize and compensate for parasitic resistance in the remote diode path.
5.14.3
Beta Compensation
The forward current gain, or beta, of a transistor is not constant as emitter currents change. As well, it is not constant over changes in temperature. The variation in beta causes an error in temperature reading that is proportional to absolute temperature. This correction is done by implementing the BJT or transistor model for temperature measurement. For discrete transistors configured with the collector and base shorted together, the beta is generally sufficiently high such that the percent change in beta variation is very small. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 50 would contribute approximately 0.25C error at 100C. However for substrate transistors where the base-emitter junction is used for temperature measurement and the collector is tied to the substrate, the proportional beta variation will cause large error. For example, a 10% variation in beta for two forced emitter currents with a transistor whose ideal beta is 0.5 would contribute approximately 8.25C error at 100C. The Beta Compensation circuitry in the EMC2106 corrects for this beta variation to eliminate any error which would normally be induced. It automatically detects the appropriate beta setting to use.
5.14.4
Digital Averaging
The External Diode 1 channel support a 4x digital averaging filter. Every cycle, this filter updates the temperature data based an a running average of the last 4 measured temperature values. The digital averaging reduces temperature flickering and increases temperature measurement stability. The digital averaging can be disabled by setting the DIS_AVG bit in the Configuration 2 Register (see Section 6.10).
5.15
Thermistor Support
The External Diode 1, External Diode 2, and External Diode 3 channels can be configured to monitor a thermistor. When this function is enabled, the data on the VIN1, VIN2, or VIN3 channels can be configured to measure a simple voltage input or a ground-connected thermistor circuit (see Appendix A for more information). The External Diode 1 channel can only be configured as a voltage input if the SHDN_SEL pin is set to a logic `1'.
5.16
Diode Connections
The diode connection for the External Diode 1 channel is determined at power-up based on the SHDN_SEL pin (see Section 5.1.1). This channel can support a diode-connected transistor (such as a 2N3904) or a substrate transistor (such as those found in an CPU or GPU) as shown in Figure 5.7. The External Diode 3 channel supports any diode connection shown or it can be configured to operate in anti-parallel diode (APD) mode. When configured in APD mode, a fourth temperature channel is available that shares the DP3 and DN3 pins. When in this mode, both the external diode 3 channel and external diode 4 channel thermal diodes must be connected as a diode.
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Diode 2
Diode 1
to DP to DN
to DP
to DP
Local Ground Typical remote substrate transistor i.e. CPU substrate PNP
to DN Typical remote discrete PNP transistor i.e. 2N3906 Typical remote discrete NPN transistor i.e. 2N3904
to DN
Anti-parallel diodes using discrete NPN transistors
Figure 5.7 Diode Connections
5.16.1
Diode Faults
The EMC2106 actively detects an open and short condition on each measurement channel. When a diode fault is detected, the temperature data MSByte is forced to a value of 80h and the FAULT bit is set in the Status Register. When the External Diode 3 channel is configured to operate in APD mode, the circuitry will detect independent open fault conditions, however a short condition will be shared between the External Diode 3 and External Diode 4 channels.
5.17
GPIOs
The EMC2106 contains up to six (6) GPIO pins (all except GPIO6 are multiplexed with other functions). The GPIO pins can be individually configured as an input or an output and as a push-pull or opendrain output. Additionally, each GPIO pin, when configured as an input, can be individually enabled to trigger an interrupt when they change states.
5.18
Interrupts
If a change of state occurs (such as a temperature out-of-limit condition or a GPIO changing states) then the following will occur: 1. The appropriate status bits will be set in the Status Register and in the High, Low, and Fault Status Registers. 2. The ALERT# will be asserted if the specific channel interrupt is enabled (see Section 6.15). The ALERT# pin is cleared by setting the MASK bit, disabling the specific interrupt channel enable, or reading the status registers. If the error conditions persist, then the status bits will remain set. Unless the Interrupt Status Enable bits are cleared or the MASK bit is set, the ALERT# pin will likewise be set.
5.19
Over Limit Outputs
The EMC2106 contains three dedicated output pins, OVERT1#, OVERT2#, and OVERT3#. Each of these pins is dedicated to reporting interrupts associated with the External Diode 1 channel, the External Diode 2 channel, and the External Diode 3 channel respectively. These interrupts work in addition to the general interrupt ALERT#.
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
The OVERT1#, OVERT2#, or OVERT3# pin will be asserted depending on which channel reported an error condition. These interrupt pins are not masked though they can be individually disabled by the user. The OVERT1#, OVERT2# and/or OVERT3# pins are cleared automatically when the measured temperature drops below the high limit minus 4C or exceeds the low limit plus 4C.
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Chapter 6 Register Set
6.1 Register Map
The following registers are accessible through the SMBus Interface. All register bits marked as `-' will always read `0'. A write to these bits will have no effect.
Table 6.1 EMC2106 Register Set REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Temperature Registers
LOCK
PAGE
00h
R
Internal Temp Reading High Byte Internal Temp Reading Low Byte External Diode 1 Temp Reading High Byte External Diode 1 Temp Reading Low Byte External Diode 2 Temp Reading High Byte External Diode 2 Temp Reading Low Byte External Diode 3 Temp Reading High Byte External Diode 3 Temp Reading Low Byte External Diode 4 Temp Reading High Byte External Diode 4 Temp Reading Low Byte Critical/Thermal Shutdown Temperature Pushed Temperature 1
Stores the integer data of the Internal Diode Stores the fractional data of the Internal Diode Stores the integer data of External Diode 1 and VIN1 channel Stores the fractional data of External Diode 1 Stores the integer data of External Diode 2 and VIN2 channel Stores the fractional data of External Diode 2 Stores the integer data of External Diode 3 and VIN3 channel Stores the fractional data of External Diode 3 Stores the integer data of External Diode 4 Stores the fractional data of External Diode 4 Stores the calculated Critical/Thermal Shutdown temperature high limit derived from the voltage on TRIP_SET / VIN4 Stores the integer data for Pushed Temperature 1 to drive LUT 1
00h
No
Page 54
01h
R
00h
No
Page 54
02h
R
00h
No
Page 54
03h
R
00h
No
Page 54
04h
R
00h
No
Page 54
05h
R
00h
No
Page 54
06h
R
00h
No
Page 54
07h
R
00h
No
Page 54
08h
R
00h
No
Page 54
09h
R
00h
No
Page 54
0Ah
R
7Fh (+127C)
No
Page 55
0Ch
R/W
00h
No
Page 56
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Table 6.1 EMC2106 Register Set (continued) REGISTER NAME Pushed Temperature 2 Pushed Temperature 3 Pushed Temperature 4 Trip Set Voltage DEFAULT VALUE 00h 00h 00h FFh
ADDR 0Dh 0Eh 0Fh 10h
R/W R/W R/W R/W R
FUNCTION Stores the integer data for Pushed Temperature 2 to drive LUT 1 Stores the integer data for Pushed Temperature 3 to drive LUT2 Stores the integer data for Pushed Temperature 4 to drive LUT2 Stores the raw measured TRIP_SET voltage or the VIN4 analog voltage input Diode Configuration
LOCK No No No No
PAGE Page 56 Page 56 Page 56 Page 56
14h
R/W
External Diode 1 Beta Configuration External Diode 2 Beta Configuration External Diode 3 Beta Configuration External Diode REC Configuration External Diode 1 Tcrit Limit External Diode 2 Tcrit Limit External Diode 3 Tcrit Limit External Diode 4 Tcrit Limit Internal Diode Tcrit Limit
Configures the beta compensation settings for External Diode 1 Configures the beta compensation settings for External Diode 2 Configures the beta compensation settings for External Diode 3 Configures the Resistance Error Correction functionality for all external diodes Stores the Critical temperature limit for the External Diode 1 Stores the Critical temperature limit for the External Diode 2 Stores the Critical temperature limit for the External Diode 3 Stores the Critical temperature limit for the External Diode 4 Stores the Critical temperature limit for the Internal Diode Configuration and control
10h
SWL
Page 57
15h
R/W
10h
SWL
Page 57
16h
R/W
10h
SWL
Page 57
17h
R/W
07h 64h (100C) 64h (100C) 64h (100C) 64h (100C) 64h (100C)
SWL Write Lock Write Lock Write Lock Write Lock Write Lock
Page 58
19h 1Ah 1Bh 1Ch 1Dh
R/W R/W R/W R/W R/W
Page 59 Page 59 Page 59 Page 59 Page 59
1Fh
R-C
Tcrit Limit Status
Stores the status bits for all temperature channel Tcrit limits Configures the Thermal / Critical Shutdown masking options and software lock Controls the conversion rate for monitoring of all channels Controls the VIN1 - 3 channels Stores the status bits for temperature channels
00h
No
Page 62
20h
R/W
Configuration
00h
SWL
Page 59
21h 22h 23h
R/W R/W R
Configuration 2 Configuration 3 Interrupt Status
0Eh 00h 00h
SWL SWL No
Page 60 Page 61 Page 62
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME High Limit Status Low Limit Status Diode Fault Fan Status Interrupt Enable Register Fan Interrupt Enable Register PWM Config PWM Base Frequency PWM 3 Frequency divide PWM3 Setting PWM4 Setting PWM4 Frequency Divide DEFAULT VALUE 00h 00h 00h 00h 00h 00h 00h FFh 50h (80) 00h 00h 50h (80)
ADDR 24h 25h 26h 27h 28h 29h 2Ah 2Bh 2Ch 2Dh 2Eh 2Fh
R/W R-C R-C R-C R-C R/W R/W R/W R/W R/W R/W R/W R/W
FUNCTION Stores the status bits for all temperature channel high limits Stores the status bits for all temperature channel low limits Stores the status bits for all temperature channel diode faults Stores the status bits for the RPM based Fan Speed Control Algorithm Controls the masking of interrupts on all temperature channels Controls the masking of interrupts on all fan related channels Configures all PWM drivers Selects the base frequency for all PWM drivers. Determines the frequency divide value for PWM driver 3 if enabled Stores the setting of the PWM3 output if enabled Stores the setting of the PWM4 output if enabled Determines the frequency divide value for PWM driver 3 if enabled Temperature Limit Registers
LOCK No No No No No No No No No No No No
PAGE Page 63 Page 63 Page 63 Page 64 Page 64 Page 65 Page 66 Page 66 Page 67 Page 67 Page 68 Page 67
30h 31h 32h 33h 34h 35h 38h 39h
R/W R/W R/W R/W R/W R/W R/W R/W
External Diode 1 Temp High Limit External Diode 2 Temp High Limit External Diode 3 Temp High Limit External Diode 4 Temp High Limit Internal Diode High Limit Voltage 4 High Limit External Diode 1 Temp Low Limit External Diode 2 Temp Low Limit
High limit for External Diode 1 or VIN1 High limit for External Diode 2 or VIN2 High limit for External Diode 3 or VIN3 High Limit for External Diode 4 High Limit for Internal Diode High Limit for the Voltage 4 channel Low Limit for External Diode 1 or VIN1 Low Limit for External Diode 2 or VIN2
55h (+85C) 55h (+85C) 55h (+85C) 55h (85C) 55h (85C) FFh (0.8V) 00h (0C) 00h (0C)
SWL SWL SWL SWL SWL SWL SWL SWL
Page 68 Page 68 Page 68 Page 68 Page 68 Page 68 Page 68 Page 68
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME External Diode 3 Temp Low Limit External Diode 4 Temp Low Limit Internal Diode Low Limit Voltage 4 Low Limit DEFAULT VALUE 00h (0C) 00h (0C) 00h (0C) 00h (0V)
ADDR 3Ah 3Bh 3Ch 3Dh
R/W R/W R/W R/W R/W
FUNCTION Low Limit for External Diode 3 or VIN3 Low Limit for External Diode 4 Low Limit for Internal Diode Low limit for Voltage 4 Channel Fan 1 Control Registers Always displays the most recent fan driver input setting for Fan 1. If the RPM based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for Fan 1 Sets configuration values for the RPM based Fan Speed Control Algorithm for the Fan 1 driver Sets additional configuration values for the Fan 1 driver Holds the gain terms used by the RPM based Fan Speed Control Algorithm for the Fan 1 driver Sets the configuration values for Spin Up Routine of the Fan 1 driver Sets the maximum change per update for the Fan 1 driver Sets the minimum drive value for the Fan 1 driver Holds the minimum tachometer reading that indicates the fan is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive Holds the target tachometer reading low byte Fan 1 Holds the target tachometer reading high byte for Fan 1 Holds the tachometer reading high byte for Fan 1
LOCK SWL SWL SWL SWL
PAGE Page 68 Page 68 Page 68 Page 68
40h
R/W
Fan 1 Setting
00h
No
Page 69
41h
R/W
PWM 1 Divide Fan 1 Configuration 1 Fan 1 Configuration 2 Gain 1 Fan 1 Spin Up Configuration Fan 1 Step Fan 1 Minimum Drive Fan 1 Valid TACH Count Fan 1 Drive Fail Band Low Byte Fan 1 Drive Fail Band High Byte TACH 1 Target Low Byte TACH 1 Target High Byte TACH 1 Reading High Byte
01h
No
Page 70
42h
R/W
2Bh
No
Page 70
43h
R/W
38h
SWL
Page 72
45h
R/W
2Ah
SWL
Page 74
46h 47h 48h
R/W R/W R/W
19h 10h 66h (40%) F5h
SWL SWL SWL
Page 75 Page 76 Page 77
49h
R/W
SWL
Page 77
4Ah 4Bh 4Ch 4Dh 4Eh
R/W R/W R/W R/W R
00h 00h F8h FFh FFh
SWL Page 78 SWL No No No Page 78 Page 78 Page 79
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Table 6.1 EMC2106 Register Set (continued) REGISTER NAME TACH 1 Reading Low Byte DEFAULT VALUE F8h
ADDR 4Fh
R/W R
FUNCTION Holds the tachometer reading low byte for Fan 1 Look Up Table 1 (LUT1)
LOCK No
PAGE Page 79
50h 51h
R/W R/W
LUT 1 Configuration LUT 1 Drive 1 LUT 1 Temp 1 Setting 1 LUT 1 Temp 2 Setting 1
Stores and controls the configuration for LUT 1 Stores the lowest programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 1 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 1 value Stores the second programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1)channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 2 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 2 value Stores the third programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 3 value
00h FBh 7Fh (127C) 7Fh (127C)
No LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 80 Page 81
52h
R/W
Page 81
53h
R/W
Page 81
54h
R/W
LUT 1 Temp 3 Setting 1
7Fh (127C)
LUT Lock 1
Page 81
55h
R/W
LUT 1 Temp 4 Setting 1
7Fh (127C)
LUT Lock 1 LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 81
56h
R/W
LUT 1 Drive 2 LUT 1 Temp 1 Setting 2 LUT 1 Temp 2 Setting 2
E6h 7Fh (127C) 7Fh (127C)
Page 81
57h
R/W
Page 81
58h
R/W
Page 81
59h
R/W
LUT 1 Temp 3 Setting 2
7Fh (127C)
LUT Lock 1
Page 81
5Ah
R/W
LUT 1 Temp 4 Setting 2
7Fh (127C)
LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 81
5Bh
R/W
LUT 1 Drive 3 LUT 1 Temp 1 Setting 3
D1h 7Fh (127C)
Page 81
5Ch
R/W
Page 81
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME LUT 1 Temp 2 Setting 3 DEFAULT VALUE 7Fh (127C)
ADDR
R/W
FUNCTION Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 3 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 3 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 3 value Stores the fourth programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 4 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 4 value Stores the fifth programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 5 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 5 value Stores the sixth programmed drive setting for LUT 1
LOCK LUT Lock 1
PAGE
5Dh
R/W
Page 81
5Eh
R/W
LUT 1 Temp 3 Setting 3
7Fh (127C)
LUT Lock 1
Page 81
5Fh
R/W
LUT 1 Temp 4 Setting 3
7Fh (127C)
LUT Lock 1 LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 81
60h
R/W
LUT 1 Drive 4 LUT 1 Temp 1 Setting 4 LUT 1 Temp 2 Setting 4
BCh 7Fh (127C) 7Fh (127C)
Page 81
61h
R/W
Page 81
62h
R/W
Page 81
63h
R/W
LUT 1 Temp 3 Setting 4
7Fh (127C)
LUT Lock 1
Page 81
64h
R/W
LUT 1 Temp 4 Setting 4
7Fh (127C)
LUT Lock 1 LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 81
65h
R/W
LUT 1 Drive 5 LUT 1 Temp 1 Setting 5 LUT 1 Temp 2 Setting 5
A7h 7Fh (127C) 7Fh (127C)
Page 81
66h
R/W
Page 81
67h
R/W
Page 81
68h
R/W
LUT 1 Temp 3 Setting 5
7Fh (127C)
LUT Lock 1
Page 81
69h
R/W
LUT 1 Temp 4 Setting 5
7Fh (127C)
LUT Lock 1 LUT Lock 1
Page 81
6Ah
R/W
LUT 1 Drive 6
92h
Page 81
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME LUT 1 Temp 1 Setting 6 LUT 1 Temp 2 Setting 6 DEFAULT VALUE 7Fh (127C) 7Fh (127C)
ADDR
R/W
FUNCTION Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 6 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 6 value Stores the seventh programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 7 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 7 value Stores the highest programmed drive setting for LUT 1 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 1 temp) that is associated with the Drive 8 value
LOCK LUT Lock 1 LUT Lock 1
PAGE
6Bh
R/W
Page 81
6Ch
R/W
Page 81
6Dh
R/W
LUT 1 Temp 3 Setting 6
7Fh (127C)
LUT Lock 1
Page 81
6Eh
R/W
LUT 1 Temp 4 Setting 6
7Fh (127C)
LUT Lock 1 LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 81
6Fh
R/W
LUT 1 Drive 7 LUT 1 Temp 1 Setting 7 LUT 1 Temp 2 Setting 7
92h 7Fh (127C) 7Fh (127C)
Page 81
70h
R/W
Page 81
71h
R/W
Page 81
72h
R/W
LUT 1 Temp 3 Setting 7
7Fh (127C)
LUT Lock 1
Page 81
73h
R/W
LUT 1 Temp 4 Setting 7
7Fh (127C)
LUT Lock 1 LUT Lock 1 LUT Lock 1 LUT Lock 1
Page 81
74h
R/W
LUT 1 Drive 8 LUT 1 Temp 1 Setting 8 LUT 1 Temp 2 Setting 8
92h 7Fh (127C) 7Fh (127C)
Page 81
75h
R/W
Page 81
76h
R/W
Page 81
77h
R/W
LUT 1 Temp 3 Setting 8
7Fh (127C)
LUT Lock 1
Page 81
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Stores the threshold level for the Internal Diode channel (or Pushed Temp 2 temp) that is associated with the Drive 8 value Stores the hysteresis that is shared for all temperature inputs Fan 2 Control Registers Always displays the most recent fan driver input setting for Fan 2. If the RPM based Fan Speed Control Algorithm is disabled, allows direct user control of the fan driver. Stores the divide ratio to set the frequency for Fan 2 Sets configuration values for the RPM based Fan Speed Control Algorithm for Fan 2 Sets additional configuration values for the Fan 2 driver Holds the gain terms used by the RPM based Fan Speed Control Algorithm for Fan 2 Sets the configuration values for Spin Up Routine of the Fan 2 driver Sets the maximum change per update for Fan 2 Sets the minimum drive value for the Fan 2 driver Holds the minimum tachometer reading that indicates the fan is spinning properly Stores the number of Tach counts used to determine how the actual fan speed must match the target fan speed at full scale drive Holds the target tachometer setting low byte for Fan 2 Holds the target tachometer setting high byte for Fan 2 Holds the tachometer reading high byte for Fan 2 Holds the tachometer reading low byte for Fan 2 Look Up Table 2 (LUT2)
LOCK
PAGE
78h
R/W
LUT 1 Temp 4 Setting 8 LUT 1 Temp Hysteresis
7Fh (127C) 0Ah (10C)
LUT Lock 1 LUT Lock 1
Page 81
79h
R/W
Page 81
80h
R/W
Fan 2 Setting
00h
No
Page 69
81h
R/W
PWM2 Divide Fan 2 Configuration1 Fan 2 Configuration 2 Gain 2 Fan 2 Spin Up Configuration Fan 2 Step Fan 2 Minimum Drive Fan 2 Valid TACH Count Fan 2 Drive Fail Band Low Byte Fan 2 Drive Fail Band High Byte TACH 2 Target Low Byte TACH 2 Target High Byte TACH 2 Reading High Byte TACH 2 Reading Low Byte
01h
No
Page 70
82h
R/W
2Bh
No
Page 70
83h
R/W
38h
SWL
Page 72
85h
R/W
2Ah
SWL
Page 74
86h 87h 88h
R/W R/W R/W
19h 10h 66h (40%) F5h
SWL SWL SWL
Page 75 Page 76 Page 77
89h
R/W
SWL
Page 77
8Ah 8Bh 8Ch 8Dh 8Eh 8Fh
R/W R/W R/W R/W R R
00h 00h F8h FFh FFh F8h
SWL Page 78 SWL No No No No Page 78 Page 78 Page 79 Page 79
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME LUT 2 Configuration LUT 2 Drive 1 LUT 2 Temp 1 Setting 1 LUT 2 Temp 2 Setting 1 DEFAULT VALUE 00h FBh 7Fh (127C) 7Fh (127C)
ADDR 90h 91h
R/W R/W R/W
FUNCTION Stores and controls the configuration for LUT 2 Stores the lowest programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 1 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 1 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 1 value Stores the second programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1)channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 2 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 2 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 2 value Stores the third programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 3 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 3 value
LOCK No LUT Lock 2 LUT Lock 2 LUT Lock 2
PAGE Page 80 Page 83
92h
R/W
Page 83
93h
R/W
Page 83
94h
R/W
LUT 2 Temp 3 Setting 1
7Fh (127C)
LUT Lock 2
Page 83
95h
R/W
LUT 2 Temp 4 Setting 1
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
96h
R/W
LUT 2 Drive 2 LUT 2 Temp 1 Setting 2 LUT 2 Temp 2 Setting 2
E6h 7Fh (127C) 7Fh (127C)
Page 83
97h
R/W
Page 83
98h
R/W
Page 83
99h
R/W
LUT 2 Temp 3 Setting 2
7Fh (127C)
LUT Lock 2
Page 83
9Ah
R/W
LUT 2 Temp 4 Setting 2
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
9Bh
R/W
LUT 2 Drive 3 LUT 2 Temp 1 Setting 3 LUT 2 Temp 2 Setting 3
D1h 7Fh (127C) 7Fh (127C)
Page 83
9Ch
R/W
Page 83
9Dh
R/W
Page 83
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
Table 6.1 EMC2106 Register Set (continued) REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 3 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 3 value Stores the fourth programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 4 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 4 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 4 value Stores the fifth programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 5 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 5 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 5 value Stores the sixth programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 6 value
LOCK
PAGE
9Eh
R/W
LUT 2 Temp 3 Setting 3
7Fh (127C)
LUT Lock 2
Page 83
9Fh
R/W
LUT 2 Temp 4 Setting 3
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
A0h
R/W
LUT 2 Drive 4 LUT 2 Temp 1 Setting 4 LUT 2 Temp 2 Setting 4
BCh 7Fh (127C) 7Fh (127C)
Page 83
A1h
R/W
Page 83
A2h
R/W
Page 83
A3h
R/W
LUT 2 Temp 3 Setting 4
7Fh (127C)
LUT Lock 2
Page 83
A4h
R/W
LUT 2 Temp 4 Setting 4
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
A5h
R/W
LUT 2 Drive 5 LUT 2 Temp 1 Setting 5 LUT 2 Temp 2 Setting 5
A7h 7Fh (127C) 7Fh (127C)
Page 83
A6h
R/W
Page 83
A7h
R/W
Page 83
A8h
R/W
LUT 2 Temp 3 Setting 5
7Fh (127C)
LUT Lock 2
Page 83
A9h
R/W
LUT 2 Temp 4 Setting 5
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
AAh
R/W
LUT 2 Drive 6 LUT 2 Temp 1 Setting 6
92h 7Fh (127C)
Page 83
ABh
R/W
Page 83
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Table 6.1 EMC2106 Register Set (continued) REGISTER NAME LUT 2 Temp 2 Setting 6 DEFAULT VALUE 7Fh (127C)
ADDR
R/W
FUNCTION Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 6 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 6 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 6 value Stores the seventh programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 7 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 7 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 7 value Stores the highest programmed drive setting for LUT 2 Stores the threshold level for the External Diode 1 (or VIN1) channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 2 (or VIN2) channel that is associated with the Drive 8 value Stores the threshold level for the External Diode 3 channel (or VIN3 or TRIP_SET voltage or Pushed Temp 3 temp) that is associated with the Drive 8 value Stores the threshold level for the Internal Diode channel (or Pushed Temp 4 temp) that is associated with the Drive 8 value Stores the hysteresis that is shared for all temperature inputs
52
LOCK LUT Lock 2
PAGE
ACh
R/W
Page 83
ADh
R/W
LUT 2 Temp 3 Setting 6
7Fh (127C)
LUT Lock 2
Page 83
AEh
R/W
LUT 2 Temp 4 Setting 6
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
AFh
R/W
LUT 2 Drive 7 LUT 2 Temp 1 Setting 6 LUT 2 Temp 2 Setting 6
92h 7Fh (127C) 7Fh (127C)
Page 83
B0h
R/W
Page 83
B1h
R/W
Page 83
B2h
R/W
LUT 2 Temp 3 Setting 6
7Fh (127C)
LUT Lock 2
Page 83
B3h
R/W
LUT 2 Temp 4 Setting 6
7Fh (127C)
LUT Lock 2 LUT Lock 2 LUT Lock 2 LUT Lock 2
Page 83
B4h
R/W
LUT 2 Drive 8 LUT 2 Temp 1 Setting 8 LUT 2 Temp 2 Setting 8
92h 7Fh (127C) 7Fh (127C)
Page 83
B5h
R/W
Page 83
B6h
R/W
Page 83
B7h
R/W
LUT 2 Temp 3 Setting 8
7Fh (127C)
LUT Lock 2
Page 83
B8h
R/W
LUT 2 Temp 4 Setting 8 LUT 2 Temp Hysteresis
7Fh (127C) 0Ah (10C)
LUT Lock 2 LUT Lock 2
Page 83
B9h
R/W
Page 83
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Table 6.1 EMC2106 Register Set (continued) REGISTER NAME DEFAULT VALUE
ADDR
R/W
FUNCTION GPIO Registers
LOCK
PAGE
E0h
R/W
Muxed Pin Configuration Register GPIO Direction Register GPIO Output Configuration Register GPIO Input Register GPIO Output Register GPIO Interrupt Enable Register GPIO Status
Controls the pin function for the pins muxed with PWMs or GPIOs Controls the GPIO direction for GPIOs 1 -6 Controls the output type GPIOs 1 - 6
01h
No
Page 84
E1h
R/W
00h
No
Page 86
E2h
R/W
00h
No
Page 86
E3h E4h E5h E6h
R R/W R/W R
Stores the inputs for GPIOs 1 - 6 Controls the output state of GPIOs 1 - 6 Enabled Interrupts for GPIOs 1 - 6 Indicates change of state for inputs on GPIOs 1 - 6 Lock Register
00h 00h 00h 00h
No No No No
Page 86 Page 87 Page 87 Page 87
EF
R/W
Software Lock
Locks all SWL registers Revision Registers
00h
SWL
Page 88
FCh FDh FEh FFh
R R R R
Product Features Product ID Manufacturer ID Revision
Stores information about which pin controlled product features are set Stores the unique Product ID Stores the Manufacturer ID Revision
00h 1Eh 5Dh 02h
No No No No
Page 88 Page 89 Page 89 Page 89
During Power-On-Reset (POR), the default values are stored in the registers. A POR is initiated when power is first applied to the part and the voltage on the VDD supply surpasses the POR level as specified in the electrical characteristics. Any reads to undefined registers will return 00h. Writes to undefined registers will not have an effect.
6.1.1
Lock Entries
The Lock Column describes the locking mechanism, if any, used for individual registers. All SWL registers are Software Locked and therefore made read-only when the LOCK bit is set.
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6.2
Temperature Data Registers
Table 6.2 Temperature Data Registers
ADDR 00h 01h
R/W R R
REGISTER Internal Diode High Byte Internal Diode Low Byte External Diode 1 High Byte VIN1
B7 Sign 0.5
B6 64 0.25
B5 32 0.125
B4 16 -
B3 8 -
B2 4 -
B1 2 -
B0 1 -
DEFAULT 00h 00h
Sign 400 0.5
64 200 0.25
32 100 0.125
16 50 -
8 25 -
4 13.5 -
2 6.25 -
1 3.125 -
00h 00h 00h
02h
R
03h
R
External Diode 1 Low Byte External Diode 2 High Byte VIN2
Sign 400 0.5
64 200 0.25
32 100 0.125
16 50 -
8 25 -
4 13.5 -
2 6.25 -
1 3.125 -
00h 00h 00h
04h
R
05h
R
External Diode 2 Low Byte External Diode 3 High Byte VIN3
Sign 400 0.5
64 200 0.25
32 100 0.125
16 50 -
8 25 -
4 13.5 -
2 6.25 -
1 3.125 -
00h 00h 00h
06h
R
07h
R
External Diode 3 Low Byte External Diode 4 High Byte External Diode 4 Low Byte
08h
R
Sign
64
32
16
8
4
2
1
00h
09h
R
0.5
0.25
0.125
-
-
-
-
-
00h
The temperature measurement range is from -64C to +128C. The data format is a signed two's complement number as shown in Table 6.3. APPLICATION NOTE: When each of the External Diode 1, External Diode 2, or External Diode 3 channels are configured as a voltage input, the voltage data will be stored in the corresponding data register. Each bit weight represents XmV of resolution so that the final voltage can be determined by adding the appropriately set bits together. This data will be compared against the limits normally (see Section 6.22).
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Table 6.3 Temperature Data Format HEX (AS READ BY REGISTERS) 80_00h C0_20h C1_00h FF_00h FF_E0h 00_00h 00_20h 01_00h 3F_00h 40_00h 41_00h 7F_00h 7F_E0h
TEMPERATURE (C) Diode Fault -63.875 -63 -1 -0.125 0 0.125 1 63 64 65 127 127.875
BINARY 1000_0000_000b 1100_0000_001b 1100_0001_000b 1111_1111_000b 1111_1111_111b 0000_0000_000b 0000_0000_001b 0000_0001_000b 0011_1111_000b 0100_0000_000b 0100_0001_000b 0111_1111_000b 0111_1111_111b
6.3
Critical/Thermal Shutdown Temperature Registers
Table 6.4 Critical/Thermal Shutdown Temperature Registers
ADDR
R/W
REGISTER Critical/Thermal Shutdown Temperature
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 7Fh (+127C)
0Ah
R
128
64
32
16
8
4
2
1
The Critical/Thermal Shutdown Temperature Register is a read-only register that stores the Voltage Programmable Threshold temperature used in the Thermal / Critical Shutdown circuitry. The contents of the register reflect the calculated temperature based on the TRIP_SET voltage. This register is updated at the end of every monitoring cycle based on the current value of the TRIP_SET voltage. The data format is shown in Table 6.5. Table 6.5 Critical / Thermal Shutdown Data Format TEMPERATURE (C) 0 1 63 64 BINARY 0000_0000b 0000_0001b 0011_1111b 0100_0000b HEX 00h 01h 3Fh 40h
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Table 6.5 Critical / Thermal Shutdown Data Format (continued) TEMPERATURE (C) 65 127 130 150 BINARY 0100_0001b 0111_1111b 1000_0010b 1001_0110b HEX 41h 7Fh 82h 96h
6.4
Pushed Temperature Registers
Table 6.6 Pushed Temperature Register
ADDR 0Ch 0Dh 0Eh 0Fh
R/W R/W R/W R/W R/W
REGISTER Pushed Temperature 1 Pushed Temperature 2 Pushed Temperature 3 Pushed Temperature 4
B7 Sign Sign Sign Sign
B6 64 64 64 64
B5 32 32 32 32
B4 16 16 16 16
B3 8 8 8 8
B2 4 4 4 4
B1 2 2 2 2
B0 1 1 1 1
DEFAULT 00h 00h 00h 00h
The Pushed Temperature Registers store user programmed temperature values that can be used by the look-up table to update the fan control algorithm. Data written in these registers is not compared against any limits and must match the data format shown in Table 6.3.
6.5
Voltage Registers
Table 6.7 TripSet Voltage Register
ADDR
R/W
REGISTER TRIP_SET Voltage / VIN4 Voltage
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
10h
R
400
200
100
50
25
13.5
6.25
3.125
FFh
The Voltage Registers hold the data read from the TRIP_SET voltage input. The TRIP_SET voltage is stored whether the TRIP_SET is used to set the Thermal / Critical Shutdown temperature or configured to act as the VIN4 input. Each bit weight represents mV of resolution so that the final voltage can be determined by adding the appropriately set bits together.
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6.6
Beta Configuration Registers
Table 6.8 Beta Configuration Registers
ADDR
R/W
REGISTER External Diode 1 Beta Configuration External Diode 2 Beta Configuration External Diode 3 Beta Configuration
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
14h
R/W
-
-
-
AUTO
BETA1[3:0]
10h
15h
R/W
-
-
-
AUTO
BETA2[3:0]
10h
16h
R/W
-
-
-
AUTO
BETA3[3:0]
10h
The Beta Configuration Registers control advanced temperature measurement features for each External Diode channel. The Beta Configuration Registers are software locked. The External Diode 1 Beta Configuration Register Is hardware locked if the SHDN_SEL pin is not set to disable the Critical / Thermal Shutdown functionality (see Table 6.1). Bit 4 - AUTO - Enables the Automatic Beta detection algorithm. `0' - The Automatic Beta detection algorithm is disabled. The BETAx[3:0] bit settings will be used to control the beta compensation circuitry. `1' (default) - The Automatic Beta detection algorithm is enabled. The circuitry will automatically detect the transistor type and beta values and configure the BETAx[3:0] bits for optimal performance. Bits 3 - 0 - BETAx[3:0] - hold a value that corresponds to a range of betas that the Beta Compensation circuitry can compensate for. These four bits will always show the current beta setting used by the circuitry. If the AUTO bit is set (default), then these bits may updated by the device with every temperature conversion. If the AUTO bit is not set, then the value of these bits is used to drive the beta compensation circuitry. In this case, these bits should be set with a value corresponding to the lowest expected value of beta for the PNP transistor being used as a temperature sensing device. See Table 6.9 for supported beta ranges. A value of 1111b indicates that the beta compensation circuitry is disabled. In this condition, the diode channels will function with default current levels and will not automatically adjust for beta variation. This mode is used when measuring a discrete 2N3904 transistor or AMD thermal diode. All of the Beta Configuration Registers are Software Locked.
Table 6.9 Beta Compensation Look Up Table BETAX[3:0] AUTO 0 0 0 0 0
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2 0 0 0 0 1
1 0 0 1 1 0
57
0 0 1 0 1 0
MINIMUM BETA 0.050 0.066 0.087 0.114 0.150
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Table 6.9 Beta Compensation Look Up Table (continued) BETAX[3:0] AUTO 0 0 0 0 0 0 0 0 0 0 0 1 3 0 0 0 1 1 1 1 1 1 1 1 X 2 1 1 1 0 0 0 0 1 1 1 1 X 1 0 1 1 0 0 1 1 0 0 1 1 X 0 1 0 1 0 1 0 1 0 1 0 1 X MINIMUM BETA 0.197 0.260 0.342 0.449 0.591 0.778 1.024 1.348 1.773 2.333 Disabled Automatically detected
6.7
REC Configuration Register
Table 6.10 REC Configuration Register
ADDR 17h
R/W R/W
REGISTER REC Configuration
B7 -
B6 -
B5 -
B4 -
B3 -
B2 REC3
B1 REC2
B0 REC1
DEFAULT 07h
The REC Configuration Register determines whether Resistance Error Correction is used for each external diode channel. The REC Configuration Register is software locked. Bit 2 - REC3 - Controls the Resistive Error Correction functionality of External Diode 3 and External Diode 4 (if APD is enabled, see Section 6.9) `0' - the REC functionality for External Diode 3 is disabled `1' (default) - the REC functionality for External Diode 3 is enabled. Bit 1 - REC2 - Controls the Resistive Error Correction functionality of External Diode 2. `0' - the REC functionality for External Diode 2 is disabled `1' (default) - the REC functionality for External Diode 2 is enabled. Bit 0 - REC1 - Controls the Resistive Error Correction functionality of External Diode 1. This bit is locked if the SHDN_SEL pin is not pulled to VDD (see Table 6.1). `0' - the REC functionality for External Diode 1 is disabled `1' (default) - the REC functionality for External Diode 1 is enabled.
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6.8
Critical Temperature Limit Registers
Table 6.11 Limit Registers
ADDR 19h 1Ah 1Bh 1Ch 1Dh
R/W R/W once R/W once R/W once R/W once R/W once
REGISTER External Diode 1 Tcrit Limit External Diode 2 Tcrit Limit External Diode 3 Tcrit Limit External Diode 4 Tcrit Limit Internal Diode Tcrit Limit
B7 Sign Sign Sign Sign Sign
B6 64 64 64 64 64
B5 32 32 32 32 32
B4 16 16 16 16 16
B3 8 8 8 8 8
B2 4 4 4 4 4
B1 2 2 2 2 2
B0 1 1 1 1 1
DEFAULT 64h (+100C) 64h (+100C) 64h (+100C) 64h (+100C) 64h (+100C)
The Critical Temperature Limit Registers store the Critical Temperature Limit. At power up, none of the respective channels are linked to the SYS_SHDN pin or the Hardware set Thermal/Critical Shutdown circuitry. Whenever one of the registers is updated, two things occur. First, the register is locked so that it cannot be updated again without a power on reset. Second, the respective temperature channel is linked to the SYS_SHDN pin and the Hardware set Thermal/Critical Shutdown Circuitry. At this point, if the measured temperature channel exceeds the Critical limit, the SYS_SHDN pin will be asserted, the appropriate bit set in the Tcrit Status Register, and the TCRIT bit in the Interrupt Status Register will be set.
6.9
Configuration Register
Table 6.12 Configuration Register
ADDR 20h
R/W R/W
REGISTER Configuration
B7 MASK
B6 -
B5 -
B4 SYS4
B3 SYS3
B2 SYS2
B1 SYS1
B0 APD
DEFAULT 00h
The Configuration Register controls the basic functionality of the EMC2106. The bits are described below. The Configuration Register is software locked. Bit 7 - MASK - Blocks the ALERT# pin from being asserted. `0' (default) - The ALERT# pin is unmasked. If any bit in either status register is set, the ALERT# pins will be asserted (unless individually masked via the Mask Register) `1' - The ALERT# pin is masked and will not be asserted. Bit 4 - SYS4 - Enables the high temperature limit for the External Diode 4 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 6.1). This bit is ignored if the DP3 / DN3 pins are configured to measure a voltage input. In this case, the External Diode 4 channel is disabled and not compared against any limits. `0' (default) - the External Diode 4 channel high limit will not be linked to the SYS_SHDN# pin. If the temperature exceeds the limit, the ALERT# pin will be asserted normally. `1' - the External Diode 4 channel high limit will be linked to the SYS_SHDN# pin. If the temperature exceeds the limit then the SYS_SHDN# pin will be asserted. The SYS_SHDN# pin will be released
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when the temperature drops below the high limit. The ALERT# pin will be asserted and released normally. Bit 3 - SYS3 - Enables the high temperature limit for the External Diode 3 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 6.1). Bit 2 - SYS2 - Enables the high temperature limit for the External Diode 2 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 6.1). Bit 1 - SYS1 - Enables the high temperature limit for the External Diode 1 channel to trigger the Critical / Thermal Shutdown circuitry (see Section 6.1). Bit 0 - APD - This bit enables the Anti-parallel diode functionality on the External Diode 3 pins (DP3 and DN3). `0' (default) - The Anti-parallel diode functionality is disabled. The External Diode 3 channel can be configured for any type of diode `1' - The Anti-parallel diode functionality is enabled. Both the External Diode 3 and 4 channels are configured to support a diode or diode connected transistor (such as a 2N3904). APPLICATION NOTE: When the APD diode is enabled, there will be a delay of a full temperature update before any comparisons and functionality associated with the External Diode 4 channel will be implemented. This includes the SYS4 bit operation, limit comparisons, and look up table comparisons.
6.10
Configuration 2 Register
Table 6.13 Configuration 2 Register
ADDR 21h
R/W R/W
REGISTER Config 2
B7 -
B6 DIS_ DYN
B5 DIS_ TO
B4 DIS_ AVG
B3
B2
B1
B0
DEFAULT 0Eh
QUEUE[1:0]
CONV[1:0]
The Configuration 2 Register controls conversion rate of the temperature monitoring as well as the fault queue. This register is software locked. Bit 6 - DIS_DYN - Disables the Dynamic Averaging Feature. `0' (default) - The Dynamic Averaging function is enabled. The conversion time for all temperature channels is scaled based on the chosen conversion rate to maximize accuracy and immunity to random temperature measurement variation. `1' - The Dynamic Averaging function is disabled. The conversion time for all temperature channels is fixed regardless of the chosen conversion rate. Bit 5 - DIS_TO - Disables the SMBus time out function for the SMBus client (if enabled). `0' (default) - The SMBus time out function is enabled. `1' - The SMBus time out function is disabled allowing the device to be fully I2C compliant. Bit 4 - DIS_AVG - Disables digital averaging of the External Diode 1 channel. `0' (default) - The External Diode 1 channel has digital averaging enabled. The temperature data is the average of the previous four measurements. `1' - The External Diode 1 channel has digital averaging disabled. The temperature data is the last measured data. Bits 3-2 - QUEUE[1:0] - Determines the number of consecutive out of limit conditions that are necessary to trigger an interrupt. Each measurement channel has a separate fault queue associated with the high limit, low limit, and diode fault condition except the internal diode.
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The Critical / Thermal Shutdown temperature has a separate fault queue that applies to the selected hardware shutdown channel (see Section 6.1.1) when compared against the threshold set by the TRIP_SET pin. APPLICATION NOTE: If the fault queue for any channel is currently active (i.e. an out of limit condition has been detected and caused the fault queue to increment) then changing the settings will not take effect until the fault queue is zeroed. This occurs by the ALERT# pin asserting or the out of limit condition being removed.
Table 6.14 Fault Queue QUEUE[1:0] 1 0 0 1 1 0 0 1 0 1 NUMBER OF CONSECUTIVE OUT OF LIMIT CONDITIONS 1 (disabled) 2 3 4 (default)
Bit 1 - 0 - CONV[1:0] - determines the conversion rate of the temperature monitoring. This conversion rate does not affect the fan driver. The supply current from VDD_3V is nominally dependent upon the conversion rate and the average current will increase as the conversion rate increases.
Table 6.15 Conversion Rate TEMPERATURE OVER SAMPLING FROM 11 BITS 0 0 1 0 1 CONVERSION RATE 1 / sec 2 / sec 4 / sec (default) Continuous DYN_DIS = `0' x8 x4 x2 x1 DYN_DIS = `1' x1 x1 x1 x1
CONV[1:0] 1 0 0 1 1
6.11
Configuration 3 Register
Table 6.16 Configuration 3 Register
ADDR 22h
R/W R/W
REGISTER Config 3
B7 -
B6 VIN4_I NV
B5 VIN3 _EN
B4 VIN3 _INV
B3 VIN2 _EN
B2 VIN2 _INV
B1 VIN1 _EN
B0 VIN1 _INV
DEFAULT 00h
The Configuration 3 Register controls the four voltage input channels. This register is software locked. Bit 6 - VIN4_INV - Determines whether the VIN4 channel data is inverted. `0' (default) - The VIN4 channel data is not inverted.
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`1' - The VIN4 channel data is inverted. The data presented to the reading registers and compared against the limits is determined as FFh - the measured input voltage. APPLICATION NOTE: If the TRIP_SET / VIN4 pin is configured to be used to set the Critical / Thermal Shutdown temperature associated with the External Diode 1 channel, then this bit cannot be set. Bit 5 - VIN3_EN - Enables the voltage mode on the External Diode 3 channel. `0' (default) - The External Diode 3 channel operates as a diode channel. `1' - The External Diode 3 channel operates as a voltage input. The DP3 / DN4 / VREF_T3 pin acts as a reference output voltage and the DN3 / DP4 /. VIN3 pin acts as a voltage input. This overrides the APD bit in the Configuration 1 Register (20h). Bit 4 - VIN3_INV - Determines whether the VIN3 channel data is inverted. Bit 3 - VIN2_EN - Enables the voltage mode on the External Diode 2 channel. Bit 2 - VIN2_INV - Determines whether the VIN2 channel data is inverted. Bit 1 - VIN1_EN - Enables the voltage mode on the External Diode 1 channel. Bit 0 - VIN1_INV - Determines whether the VIN1 channel data is inverted. APPLICATION NOTE: If the TRIP_SET / VIN4 pin is configured to be used to set the Critical / Thermal Shutdown temperature associated with the External Diode 1 channel, then neither Bit 1 nor Bit 0 can be set.
6.12
Interrupt Status Register
Table 6.17 Interrupt Status Register
ADDR
R/W
REGISTER Interrupt Status Register
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
23h
R-C
EEPR OM
TSD
TCRIT
GPIO
FAN
HIGH
LOW
FAULT
00h
The Interrupt Status Register reports the operating condition of the EMC2106. If any of the bits are set to a logic `1' (other than TSD and HWS) then the ALERT# pin will be asserted low if the corresponding channel is enabled. Reading from the status register clears all status bits if the error conditions is removed. If there are no set status bits, then the ALERT# pin will be released. The bits that cause the ALERT# pin to be asserted can be masked based on the channel they are associated with unless stated otherwise. Bit 7 - EEPROM - This bit is set to `1' if the EEPROM loader circuitry detects an error when writing data from the EEPROM. This bit is cleared when the register is read. This bit is not masked except via the MASK bit. Bit 6 - TSD - This bit is set to `1' if the internal Thermal Shutdown (TSD) circuit trips indicating that the die temperature has exceeded its threshold. When this bit is set, it will not cause the ALERT# pin to be asserted however will coincide with the SYS_SHDN# pin being asserted. This bit is cleared when the register is read and the error condition has been removed. Bit 5 - TCRIT - This bit is set to `1' whenever the any bit in the Tcrit Status Register is set. This bit is automatically cleared when the Tcrit Status Register is cleared. Bit 4 - GPIO - This bit is set to `1' if any of the bits in the GPIO Status Registers are set. Bit 3 - FAN - This bit is set to `1' if any bit in the Fan Status Register is set. This bit is automatically cleared when the Fan Status Register is read and the bits are cleared.
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Bit 2 - HIGH - This bit is set to `1' if any bit in the High Status Register is set. This bit is automatically cleared when the High Status Register is read and the bits are cleared. Bit 1- LOW - This bit is set to `1' if any bit in the Low Status Register is set. This bit is automatically cleared when the Low Status Register is read and the bits are cleared. Bit 0 - FAULT - This bit is set to `1' if any bit in the Diode Fault Register is set. This bit is automatically cleared when the Diode Fault Register is read and the bits are cleared.
6.13
Error Status Registers
Table 6.18 Error Status Register
ADDR 1Fh 24h 25h 26h
R/W R-C R-C R-C R-C
REGISTER Tcrit Status High Status Low Status Diode Fault
B7 HWS -
B6 -
B5 VOLT 4_HI VOLT 4_LO -
B4 EXT4_ CRIT EXT4_ HI EXT4_ LO EXT4_ FLT
B3 EXT3_ CRIT EXT3_ HI EXT3_ LO EXT3_ FLT
B2 EXT2_ CRIT EXT2_ HI EXT2_ LO EXT2_ FLT
B1 EXT1 _CRIT EXT1 _HI EXT1 _LO EXT1 _FLT
B0 INT_ CRIT INT_ HI INT_L O -
DEFAULT 00h 00h 00h 00h
The Error Status Registers report the specific error condition for all measurement channels with limits. If any bit is set in the High, Low, or Diode Fault Status register, the corresponding High, Low, or Fault bit is set in the Interrupt Status Register. Reading the Interrupt Status Register does not clear the Error Status bit. Reading from any Error Status Register that has bits set will clear the register and the corresponding bit in the Interrupt Status Register if the error condition has been removed. If the error condition is persistent, reading the Error Status Registers will have no affect. If any of the External Diode 1, External Diode 2, or External Diode 3 channels are configured as a voltage input, then the corresponding temperature channel status bit will be set if the measured voltage exceeds the high limit or falls below the low limit. In this condition, a diode fault will be ignored. APPLICATION NOTE: If any of the External Diode 1, 2, or 3 channels are configured as a voltage input and thermistor or other voltage source is used on the corresponding pins at device power up, then the corresponding diode fault status bits will be set. The status bits should be cleared prior to enabling the interrupts to avoid erroneous alert conditions.
6.13.1
Tcrit Status Register
The Tcrit Status Register stores the event that caused the SYS_SHDN# pin to be asserted. Each of the temperature channels must be associated with the SYS_SHDN# pin before they can be set (see Section 6.8). Once the SYS_SHDN# pin is asserted, it will be released when the temperature drops below the threshold level however the individual status bit will not be cleared until read. Bit 7 - HWS - This bit is set if the hardware set temperature channel meets or exceeds the temperature threshold determined by the TRIP_SET voltage.
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Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown Datasheet
6.14
Fan Status Register
Table 6.19 Fan Status Register
ADDR 27h
R/W R-C
REGISTER Fan Status Register
B7 WATCH
B6 DRIVE _FAIL2
B5 DRIVE _FAIL1
B4 FAN_ SHORT
B3 FAN_ SPIN2
B2 FAN_ STALL2
B1 FAN_ SPIN1
B0 FAN_ STALL1
DEFAULT 00h
The Fan Status Register contains the status bits associated with each fan driver. This register is cleared when read if the error condition has been removed. Bit 7 - WATCH - This bit is asserted `1' if the host has not programmed the fan driver(s) within four (4) seconds after power up. Bit 6 - DRIVE_FAIL2 - Indicates that the RPM based Fan Speed Control Algorithm cannot drive Fan 2 to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT# pin. `0' - The RPM based Fan Speed Control Algorithm can drive Fan 2 to the desired target setting. `1' - The RPM based Fan Speed Control Algorithm cannot drive Fan 2 to the desired target setting at maximum drive. Bit 6 - DRIVE_FAIL1 - Indicates that the RPM based Fan Speed Control Algorithm cannot drive Fan 1 to the desired target setting at maximum drive. This bit can be masked from asserting the ALERT# pin. `0' - The RPM based Fan Speed Control Algorithm can drive Fan 1 to the desired target setting. `1' - The RPM based Fan Speed Control Algorithm cannot drive Fan 1 to the desired target setting at maximum drive. Bit 5 - FAN_SHORT - This bit is asserted `1' if the High Side Fan Driver detects an over current condition that lasts for longer than 2 seconds. Bit 3 - FAN_SPIN 2- This bit is asserted `1' if the Spin up Routine for Fan 2 cannot detect a valid tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT# pin. Bit 2 - FAN_STALL 2 - This bit is asserted `1' if the tachometer measurement on Fan 2 detects a stalled fan. This bit can be masked from asserting the ALERT# pin. Bit 1- FAN_SPIN1- This bit is asserted `1' if the Spin up Routine for Fan 1 cannot detect a valid tachometer reading within its maximum time window. This bit can be masked from asserting the ALERT# pin. Bit 0 - FAN_STALL1 - This bit is asserted `1' if the tachometer measurement on Fan 1 detects a stalled fan. This bit can be masked from asserting the ALERT# pin.
6.15
Interrupt Enable Register
Table 6.20 Interrupt Enable Register
ADDR 28
R/W R/W
REGISTER Interrupt Enable
B7 -
B6 -
B5 VOLT4_I NT_EN
B4 EXT4_I NT_EN
B3 EXT3_I NT_EN
B2 EXT2_I NT_EN
B1 EXT1_I NT_EN
B0 INT_IN T_EN
DEFAULT 00h
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The Interrupt Enable Register controls the masking for each temperature channel. When a channel is masked, it will not cause the ALERT# pin to be asserted when an error condition is detected. Bit 5 - VOLT4_INT_EN - Allows the Voltage Input 4 channel to assert the ALERT# pin. `0' (default) - The ALERT# pin will be not be asserted for any error condition associated with Voltage Channel 4 (TRIP_SET / VIN4). `1' - The ALERT# pin will be asserted for an error condition associated with Voltage Channel 4. Bit 4 - EXT4_INT_EN - Allows the External Diode 4 channel to assert the ALERT# pin. `0' (default) - The ALERT# pin will be not be asserted for any error condition associated with External Diode 4. `1' - The ALERT# pin will be asserted for an error condition associated with External Diode 4. Bit 3 - EXT3_INT_EN - Allows the External Diode 3 or VIN3 channel to assert the ALERT# pin. `0' (default) - The ALERT# pin will not be asserted for any error condition associated with External Diode 3 or VIN3 channels. `1' - The ALERT# pin will be asserted for an error condition associated with External Diode 3 or VIN3 channels. Bit 2 - EXT2_INT_EN - Allows the External Diode 2 or VIN2 channel to assert the ALERT# pin. `0' (default) - The ALERT# pin will not be asserted for any error condition associated with External Diode 2 or VIN2 channels. `1' - The ALERT# pin will be asserted for an error condition associated with External Diode 2 or VIN2 channels. Bit 1 - EXT1_INT_EN - Allows the External Diode 1 or VIN1 channel to assert the ALERT# pin. `0' (default) - The ALERT# pin will not be asserted for any error condition associated with External Diode 1 or VIN1 channels. `1' - The ALERT# pin will be asserted for an error condition associated with External Diode 1 or VIN1 channels. Bit 0 - INT_INT_EN - Allows the Internal Diode channel to assert the ALERT# pin. `0' (default) - The ALERT# pin will not be asserted for any error condition associated with the Internal Diode. `1' - The ALERT# pin will be asserted for an error condition associated with the Internal Diode.
6.16
Fan Interrupt Enable Register
Table 6.21 Fan Interrupt Enable Register
ADDR
R/W
REGISTER Fan Interrupt Enable
B7
B6
B5
B4
B3 SPIN_ INT_EN2
B2 STALL_ INT_EN2
B1 SPIN_ INT_EN 1
B0 STALL_ INT_EN 1
DEFAULT
29h
R/W
-
-
-
-
00h
The Fan Interrupt Enable controls the masking for each Fan channel. When a channel is enabled, it will cause the ALERT# pin to be asserted when an error condition is detected. Bit 3 - SPIN_INT_EN2 - Allows the FAN_SPIN 2 bit to assert the ALERT# pin. `0' (default) - the FAN_SPIN 2 bit will not assert the ALERT# pin though will still update the Status Register normally `1' - the FAN_SPIN2 bit will assert the ALERT# pin.
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Bit 2 - STALL_INT_EN2 - Allows the FAN_STALL2 bit or DRIVE_FAIL2 bit to assert the ALERT# pin. `0' (default) - the FAN_STALL2 bit or DRIVE_FAIL2 bit will not assert the ALERT# pin though it will still update the Status Register normally. `1' - the FAN_STALL 2 or DRIVE_FAIL2 bits will assert the ALERT# pin if set. Bit 1 - SPIN_INT_EN1 - Allows the FAN_SPIN1 bit to assert the ALERT# pin. `0' (default) - the FAN_SPIN1 bit will not assert the ALERT# pin though it will still update the Status Register normally. `1' - the FAN_SPIN1 bit will assert the ALERT# pin. Bit 0 - STALL_INT_EN1 - Allows the FAN_STALL1 bit or DRIVE_FAIL1 bit to assert the ALERT# pin. `0' (default) - the FAN_STALL1 bit or DRIVE_FAIL1 bit will not assert the ALERT# pin though will still update the Status Register normally. `1' - the FAN_STALL1 or DRIVE_FAIL1 bit will assert the ALERT# pin if set.
6.17
PWM Configuration Register
Table 6.22 PWM Configuration Register
ADDR 2Ah
R/W R/W
REGISTER PWM Config
B7 -
B6 -
B5 -
B4 -
B3 POLA RITY4
B2 POLA RITY3
B1 POLA RITY2
B0 POLA RITY1
DEFAULT 00h
The PWM Config Register controls the output type and polarity of all PWM outputs. Bit 3 - POLARITY4 - Determines the polarity of PWM4 (if enabled). `0' (default) - the Polarity of the PWM driver is normal. A drive setting of 00h will cause the output to be set at 0% duty cycle and a drive setting of FFh will cause the output to be set at 100% duty cycle. `1' - The Polarity of the PWM driver is inverted. A drive setting of 00h will cause the output to be set at 100% duty cycle and a drive setting of FFh will cause the output to be set at 0% duty cycle. Bit 2 - POLARITY3 - Determines the polarity of PWM3 (if enabled). Bit 1 - POLARITY2 - Determines the polarity of PWM2 (if enabled). Bit 0 - POLARITY1 - Determines the polarity of PWM1 (if enabled).
6.18
PWM Base Frequency Register
Table 6.23 PWM Base Frequency Register
ADDR
R/W
REGISTER PWM Base Frequency
B7 PWM_ BASE 4_1
B6 PWM_ BASE 4_0
B5 PWM_ BASE 3_1
B4 PWM_ BASE 3_0
B3 PWM_ BASE 2_1
B2 PWM_ BASE 2_0
B1 PWM_ BASE 1_1
B0 PWM_ BASE 1_0
DEFAULT
2Bh
R/W
FFh
The PWM Base Frequency Register determines the base frequency that is used with the PWM Divide register to determine the final PWM frequency. Each PWM driver uses the same divide ratio as set by the PWM Divide Register.
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Bits 7-6 - PWM_BASE4[1:0] - Determines the base frequency of the PWM4 driver (GPIO3 / PWM4 pin). Bits 5-4 - PWM_BASE3[1:0] - Determines the base frequency of the PWM3 driver (GPIO2 / PWM3 pin). Bits 3-2 - PWM_BASE2[1:0] - Determines the base frequency of the PWM2 driver (PWM2 / GPIO4 pin). Bits 1-0 - PWM_BASE1[1:0] - Determines the base frequency of the PWM1 driver (PWM1).
Table 6.24 PWM_BASEx[1:0] Bit Decode PWM_BASEX[1:0] 1 0 0 1 1 0 0 1 0 1 BASE FREQUENCY 26.00kHz 19.531kHz 4,882Hz 2,441Hz (default)
6.19
PWM 3 and 4 Divide Registers
Table 6.25 PWM Divide Registers
ADDR 2Ch 2Fh
R/W R/W R/W
REGISTER PWM 3 Divide PWM 4 Divide
B7 128 128
B6 64 64
B5 32 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 50h (80) 50h (80)
The PWM 3 and PWM 4 Divide Registers determine the final frequency of the PWM 3 and PWM 4 drivers respectively. Each driver base frequency is divided by the value of the PWM Divide Register to determine the final frequency. The duty cycle settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h will be decoded as 01h.
6.20
PWM 3 Setting Register
Table 6.26 PWM 3 Setting Register
ADDR 2Dh
R/W R/W
REGISTER PWM 3 Setting
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 00h
The PWM 3 Input Register controls the output of the GPIO2 / PWM3 pin when it is configured as a PWM output. The input code represents the number of counts out of a total of 255 that the output will be high for.
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The setting operates independently of the PWM polarity A value of FFh corresponds to fully on (default 100% duty cycle) while a value of 00h corresponds to a fully off (default 0% duty cycle).
6.21
PWM 4 Setting Register
Table 6.27 PWM 4 Setting Register
ADDR 2Eh
R/W R/W
REGISTER PWM 4 Setting
B7 128
B6 64
B5 32
B4 16
B3 8
B2 4
B1 2
B0 1
DEFAULT 00h
The PWM 4 Input Register controls the output of the GPIO3 / PWM4 pin when it is configured as a PWM output. The input code represents the number of counts out of a total of 255 that the output will be high for. The setting operates independently of the PWM polarity A value of FFh corresponds to fully on (default 100% duty cycle) while a value of 00h corresponds to a fully off (default 0% duty cycle).
6.22
Limit Registers
Table 6.28 Limit Registers
ADDR 30h 31h 32h 33h 34h 35h 38h 39h 3Ah 3Bh
R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
REGISTER External Diode 1 High Limit External Diode 2 High Limit External Diode 3 High Limit External Diode 4 High Limit Internal Diode High Limit VIN4 High Limit External Diode 1 Low Limit External Diode 2 Low Limit External Diode 3 Low Limit External Diode 4 Low Limit
B7 Sign Sign Sign Sign Sign 752.9 Sign Sign Sign Sign
B6 64 64 64 64 64 376.5 64 64 64 64
B5 32 32 32 32 32 188.2 32 32 32 32
B4 16 16 16 16 16 94.12 16 16 16 16
B3 8 8 8 8 8 47.06 8 8 8 8
B2 4 4 4 4 4 23.53 4 4 4 4
B1 2 2 2 2 2 11.76 2 2 2 2
B0 1 1 1 1 1 5.88 1 1 1 1
DEFAULT 55h (+85C) 55h (+85C) 55h (+85C) 55h (+85C) 55h (+85C) FFh (0.8V) 00h (0C) 00h (0C) 00h (0C) 00h (0C)
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Table 6.28 Limit Registers (continued) ADDR 3Ch 3Dh R/W R/W R/W REGISTER Internal Diode Low Limit VIN 4 Low Limit B7 Sign 752.9 B6 64 376.5 B5 32 188.2 B4 16 94.12 B3 8 47.06 B2 4 23.53 B1 2 11.76 B0 1 5.88 DEFAULT 00h (0C) 00h (0V)
The EMC2106 contains high limits for all temperature channels and voltage channels. If any measurement meets or exceeds the high limit then the appropriate status bit is set and the ALERT# pin are asserted (if enabled). APPLICATION NOTE: If any of the External Diode 1, External Diode 2, External Diode 3 is configured to operate as a voltage input, then the corresponding temperature high and low limit registers are compared against the measured voltage. The data format is the same as the measured voltage and these registers should be updated accordingly. Additionally, the EMC2106 contains low limits for all temperature channels. If the temperature channel drops below the low limit, then the appropriate status bit is set and the ALERT# pin are asserted (if enabled). All Limit Registers are Software Locked.
6.23
Fan Setting Registers
Table 6.29 Fan Driver Setting Register
ADDR 40h 80h
R/W R/W R/W
REGISTER Fan 1 Setting Fan 2 Setting
B7 128 128
B6 64 64
B5 32 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 00h 00h
The Fan 1 Setting Register always displays the current setting of the Fan 1 Driver. Likewise, the Fan 2 Setting Register always displays the current setting of the Fan 2 driver. Reading from either register will report the current fan speed setting of the appropriate fan driver regardless of the operating mode. Therefore it is possible that reading from this register will not report data that was previously written into this register. While the RPM based Fan Speed Control Algorithm or the Look Up Table are active (or both), then the register is read only. Writing to the register will have no affect and the data will not be stored. If both the RPM based Fan Control Algorithm and the Look Up Table are disabled, then the register will be set with the previous value that was used. The register is read / write and writing to this register will affect the fan speed. If the Fan 2 fan driver is disabled and the DAC2 / PWM2 / GPIO2 and TACH2 / GPIO1 pins are used as GPIOs, then the Fan 2 Setting Register will read 00h. The contents of the register represent the weighting of each bit in determining the final output voltage. The output drive for a PWM output is given by Equation [2]. The output drive for the Linear DAC driver is given by Equation [3].The output drive for the High Side Fan Driver output is given by Equation [4].
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VALUE Drive = -------------------- x 100% 255 VALUE Drive = -------------------- x VDD 255 VALUE Drive = -------------------- x VDD_5V 255
[2]
[3]
[4]
6.24
PWM 1 and 2 Divide Registers
Table 6.30 PWM 1 and 2 Divide Registers
ADDR 41h 81h
R/W R/W R/W
REGISTER PWM 1 Divide PWM 2 Divide
B7 128 128
B6 64 64
B5 32 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 01h 01h
The PWM 1 and 2 Divide Registers determine the final frequency of the PWM 1and PWM 2 drivers. Each driver base frequency is divided by the value of the respective PWM Divide Register to determine the final frequency. The duty cycle settings are not affected by these settings, only the final frequency of the PWM driver. A value of 00h will be decoded as 01h.
6.25
Fan Configuration 1 Registers
Table 6.31 Fan Configuration 1 Registers
ADDR
R/W
REGISTER Fan 1 Configuration 1 Fan 2 Configuration 1
B7 EN_ ALGO EN_ ALGO
B6
B5
B4
B3
B2
B1
B0
DEFAULT
42h
R/W
RANGE[1:0]
EDGES[1:0]
UPDATE[2:0]
2Bh
82h
R/W
RANGE[1:0]
EDGES[1:0]
UPDATE[2:0]
2Bh
The Fan Configuration 1 Register controls the general operation of the RPM based Fan Speed Control Algorithm used for the Fan 1 driver. Bit 7 - EN_ALGO - enables the RPM based Fan Speed Control Algorithm. This bit is set and cleared automatically when the LUT_LOCK bit is set based on the setting of the TACH / DRIVE bit (see Section 6.35). When the LUT_LOCK bit is cleared, then setting this bit will enable the FSC without using the Look Up Table. `0' - (default) the control circuitry is disabled and the fan driver output is determined by the Fan Driver Setting Register. `1' - the control circuitry is enabled and the Fan Driver output will be automatically updated to maintain the programmed fan speed as indicated by the TACH Target Register.
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Bits 6- 5 - RANGE[1:0] - Adjusts the range of reported and programmed tachometer reading values. The RANGE bits determine the weighting of all TACH values (including the Valid TACH Count, TACH Target, and TACH reading) as shown in Table 6.32.
Table 6.32 Range Decode RANGE[1:0] 1 0 0 1 1 0 0 1 0 1 REPORTED MINIMUM RPM 500 1000 (default) 2000 4000 TACH COUNT MULTIPLIER 1 2 4 8
Bits 4-3 - EDGES[1:0] - determines the minimum number of edges that must be detected on the TACHx signal to determine a single rotation. A typical fan measured 5 edges (for a 2-pole fan). For more accurate tachometer measurement, the minimum number of edges measured may be increased. Increasing the number of edges measured with respect to the number of poles of the fan will cause the TACH Reading registers to indicate a fan speed that is higher or lower than the actual speed. In order for the FSC Algorithm to operate correctly, the TACH Target must be updated by the user to accommodate this shift. The Effective Tach Multiplier shown in Table 6.33 is used as a direct multiplier term that is applied to the Actual RPM to achieve the Reported RPM. It should only be applied if the number of edges measured does not match the number of edges expected based on the number of poles of the fan (which is fixed for any given fan). Contact SMSC for recommended settings when using fans with more or less than 2 poles.
Table 6.33 Minimum Edges for Fan Rotation EDGES[1:0] 1 0 0 1 1 0 1 0 1 0 MINIMUM TACH EDGES 3 5 7 9 NUMBER OF FAN POLES 1 pole 2 poles (default) 3 poles 4 poles EFFECTIVE TACH MULTIPLIER (BASED ON 2 POLE FANS) 0.5 1 1.5 2
Bit 2-0 - UPDATE - determines the base time between fan driver updates. The Update Time, along with the Fan Step Register, is used to control the ramp rate of the drive response to provide a cleaner transition of the actual fan operation as the desired fan speed changes. The Update Time is set as shown in Table 6.34.
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Table 6.34 Update Time UPDATE[2:0] 2 0 0 0 0 1 1 1 1 1 0 0 1 1 0 0 1 1 0 0 1 0 1 0 1 0 1 UPDATE TIME 100ms 200ms 300ms 400ms (default) 500ms 800ms 1200ms 1600ms
6.26
Fan Configuration 2 Registers
Table 6.35 Fan Configuration 1 Registers
ADDR
R/W
REGISTER Fan 1 Configuration 2 Fan 2 Configuration 2
B7
B6 EN_ RRC1 EN_ RRC2
B5 GLITCH _EN1 GLITCH _EN2
B4
B3
B2
B1
B0 LOWD RIVE1 LOWD RIVE2
DEFAULT
43h
R/W
-
DER_OPT1 [1:0]
ERR_RNG[1:0]
38h
83h
R/W
-
DER_OPT2 [1:0]
ERR_RNG[1:0]
38h
The Fan Configuration 2 Register controls the tachometer measurement and advanced features of the RPM based Fan Speed Control Algorithm. Bit 6 - EN_RRCx - Enables ramp rate control when the corresponding fan driver is operated in the Direct Setting Mode or the Direct Setting with LUT mode. `0' (default) - Ramp rate control is disabled. When the fan driver is operating in Direct Setting mode or Direct Setting with LUT mode, the fan setting will instantly transition to the next programmed setting. `1' - Ramp rate control is enabled. When the fan driver is operating in Direct Setting mode or Direct Setting with LUT mode, the fan drive setting will follow the ramp rate controls as determined by the Fan Step and Update Time settings. The maximum fan drive setting step is capped at the Fan Step setting and is updated based on the Update Time as given by Table 6.34. Bit 5 - GLITCH_ENx - Disables the low pass glitch filter that removes high frequency noise injected on the TACHx pin. If the LOWDRIVE bit is set, this bit is ignored and the filter is automatically disabled. `0' - The glitch filter is disabled. `1' (default) - The glitch filter is enabled. Bits 4 - 3 - DER_OPTx[1:0] - Control some of the advanced options that affect the derivative portion of the RPM based Fan Speed Control Algorithm as shown in Table 6.36.
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Table 6.36 Derivative Options DER_OPTX[1:0] 1 0 0 0 OPERATION No derivative options used Basic derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive Register setting (in addition to proportional and integral terms) Step derivative. The derivative of the error from the current drive setting and the target is added to the iterative Fan Drive Register setting and is not capped by the Fan Step Register. Both the basic derivative and the step derivative are used effectively causing the derivative term to have double the effect of the derivative term (default).
0
1
1
0
1
1
Bit 2 - 1 - ERR_RNGx[1:0] - Control some of the advanced options that affect the error window. When the measured fan speed is within the programmed error window around the target speed, then the fan drive setting is not updated. The algorithm will continue to monitor the fan speed and calculate necessary drive setting changes based on the error, however these changes are ignored.
Table 6.37 Error Range Options ERR_RNGX[1:0] 1 0 0 1 1 0 0 1 0 1 OPERATION 0 RPM (default) 50 RPM 100 RPM 200 RPM
Bit 0 - LOWDRIVEx - Determines whether the tachometer measurement circuit will use the Tach Period Measurement method of fan speed measurement or the Tach Pulse Count Method of fan speed measurement. Setting this bit allows the use of low side fan drive circuits as shown in Figure 6.1 without requiring additional tachometer recovery circuitry. `0' (default) - The tachometer signal must always be present when measuring the fan speed regardless of the measurement method. `1' - Low side PWM drive circuits are supported and the tachometer signal does not need to be present at all times (which is common with such drive techniques). The tachometer measurement circuitry will use the Tach Pulse Count Method to determine the fan speed (contact SMSC for details on this operation). All tachometer related data is in the form of edge counts over a fixed time period. This method is significantly slower and the tachometer updates are non-continuous.
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PWM Input
Figure 6.1 LOWDRIVE Supported Drive Circuit
6.27
Gain Registers
Table 6.38 Gain Registers
ADDR 45h 85h
R/W R/W R/W
REGISTER Gain 1 Register Gain 2 Register
B7 -
B6 -
B5
B4
B3
B2
B1
B0
DEFAULT 2Ah 2Ah
GAIND[1:0] GAIND[1:0]
GAINI[1:0] GAINI[1:0]
GAINP[1:0] GAINP[1:0]
The Gain Register stores the gain terms used by the proportional and integral portions of each of the RPM based Fan Speed Control Algorithms. These gain terms are used as the KD, KI, and KP gain terms in a classic PID control solution.
Table 6.39 Gain Decode GAIND OR GAINP OR GAINI [1:0] 1 0 0 1 1 0 0 1 0 1 RESPECTIVE GAIN FACTOR 1x 2x 4x (default) 8x
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6.28
Fan Spin Up Configuration Registers
Table 6.40 Fan Spin Up Configuration Registers
ADDR 46h 86h
R/W R/W R/W
REGISTER Fan 1 Spin Up Configuration Fan 2 Spin up Configuration
B7
B6
B5 NOK ICK1 NOK ICK2
B4
B3
B2
B1
B0
DEFAULT 0Dh 0Dh
DRIVE_FAIL _CNT1 [1:0] DRIVE_FAIL _CNT2 [1:0]
SPIN_LVL[2:0] SPIN_LVL[2:0]
SPINUP_TIM E [1:0] SPINUP_TIM E [1:0]
The Fan Spin Up Configuration Register controls the settings of Spin Up Routine. The Fan Spin Up Configuration Register is software locked. Bit 7 - 6 - DRIVE_FAIL_CNTx[1:0] - Determines how many update cycles are used for the Drive Fail detection function as shown in Table 6.41. This circuitry determines whether the fan can be driven to the desired tach target.
Table 6.41 DRIVE_FAIL_CNT[1:0] Bit Decode DRIVE_FAIL_CNT[1:0] 1 0 0 1 1 0 1 0 1 0 NUMBER OF UPDATE PERIODS Disabled - the Drive Fail detection circuitry is disabled (default) 16 - the Drive Fail detection circuitry will count for 16 update periods 32 - the Drive Fail detection circuitry will count for 32 update periods 64 - the Drive Fail detection circuitry will count for 64 update periods
Bit 5 - NOKICKx - Determines if the Spin Up Routine will drive the fan to 100% duty cycle for 1/4 of the programmed spin up time before driving it at the programmed level. `0' (default) - The Spin Up Routine will drive the fan driver to 100% for 1/4 of the programmed spin up time before reverting to the programmed spin level. `1' - The Spin Up Routine will not drive the fan driver to 100%. It will set the drive at the programmed spin level for the entire duration of the programmed spin up time. Bits 4 - 2 - SPIN_LVL[2:0] - Determines the final drive level that is used by the Spin Up Routine as shown in Table 6.42.
Table 6.42 Spin Level SPIN_LVL[2:0] 2 0 0 1 0 0 0 0 1 SPIN UP DRIVE LEVEL 30% 35%
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Table 6.42 Spin Level (continued) SPIN_LVL[2:0] 2 0 0 1 1 1 1 1 1 1 0 0 1 1 0 0 1 0 1 0 1 SPIN UP DRIVE LEVEL 40% 45% 50% 55% 60% (default) 65%
Bit 1 -0 - SPINUP_TIME[1:0] - determines the maximum Spin Time that the Spin Up Routine will run for (see Section 6.9). If a valid tachometer measurement is not detected before the Spin Time has elapsed, then an interrupt will be generated. When the RPM based Fan Speed Control Algorithm is active, the fan driver will attempt to re-start the fan immediately after the end of the last spin up attempt. The Spin Time is set as shown in Table 6.43.
Table 6.43 Spin Time SPINUP_TIME[1:0] 1 0 0 1 1 0 0 1 0 1 TOTAL SPIN UP TIME 250 ms 500 ms (default) 1 sec 2 sec
6.29
Fan Step Registers
Table 6.44 Fan Step Registers
ADDR 47h 87h
R/W R/W R/W
REGISTER Fan 1 Max Step Fan 2 Max Step
B7 -
B6 -
B5 32 32
B4 16 16
B3 8 8
B2 4 4
B1 2 2
B0 1 1
DEFAULT 10h 10h
The Fan Step Registers, along with the Update Time, controls the ramp rate of the fan driver response calculated by the RPM based Fan Speed Control Algorithm. The value of the registers represents the maximum step size each fan driver will take between update times (see Section 6.25). When the FSC alogorithm is enabled, Ramp Rate control is automatically used. When the FSC is not active, then Ramp Rate control can be enabled by asserting the EN_RRC bit (see Section 6.26)
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APPLICATION NOTE: The UPDATE bits and Fan Step Register settings operate independently of the RPM based Fan Speed Control Algorithm and will always limit the fan drive setting. That is, if the programmed fan drive setting (either in determined by the RPM based Fan Speed Control Algorithm, the Look Up Table, or by manual settings) exceeds the current fan drive setting by greater than the Fan Step Register setting, the EMC2106 will limit the fan drive change to the value of the Fan Step Register. It will use the Update Time to determine how often to update the drive settings. APPLICATION NOTE: If the Fan Speed Control Algorithm is used, the default settings in the Fan Configuration 2 Register will cause the maximum fan step settings to be ignored. The Fan Step Registers are software locked.
6.30
Fan Minimum Drive Registers
Table 6.45 Minimum Fan Drive Registers
ADDR
R/W
REGISTER Fan 1 Minimum Drive Fan 2 Minimum Drive
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 66h (40%) 66h (40%)
48h
R/W
128
64
32
16
8
4
2
1
88h
R/W
128
64
32
16
8
4
2
1
The Fan Minimum Drive Register stores the minimum drive setting for each RPM based Fan Speed Control Algorithm. The RPM based Fan Speed Control Algorithm will not drive the fan at a level lower than the minimum drive unless the target Fan Speed is set at FFh (see Section 6.33) During normal operation, if the fan stops for any reason (including low drive), the RPM based Fan Speed Control Algorithm will attempt to restart the fan. Setting the Fan Minimum Drive Registers to a setting that will maintain fan operation is a useful way to avoid potential fan oscillations as the control circuitry attempts to drive it at a level that cannot support fan operation. The Fan Minimum Drive Register is software locked.
6.31
Valid TACH Count Registers
Table 6.46 Valid TACH Count Registers
ADDR 49h 89h
R/W R/W R/W
REGISTER Valid TACH Count 1 Valid TACH Count 2
B7 4096 4096
B6 2048 2048
B5 1024 1024
B4 512 512
B3 256 256
B2 128 128
B1 64 64
B0 32 32
DEFAULT F5h F5h
The Valid TACH Count Register stores the maximum TACH Reading Register value to indicate that the each fan is spinning properly. The value is referenced at the end of the Spin Up Routine to determine if the fan has started operating and decide if the device needs to retry. See Equation [5] for translating the count to an RPM. This register is only used when the FSC is active.
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If the TACH Reading Register value exceeds the Valid TACH Count Register (indicating that the Fan RPM is below the threshold set by this count), then a stalled fan is detected. In this condition, the algorithm will automatically begin its Spin Up Routine. If a TACH Target setting is set above the Valid TACH Count setting, then that setting will be ignored and the algorithm will use the current fan drive setting. The Valid TACH Count Register is software locked.
6.32
Fan Drive Fail Band Registers
Table 6.47 Fan Drive Fail Band Registers
ADDR
R/W
REGISTER Fan 1 Drive Fail Band Low Byte Fan 1 Drive Fail Band High Byte Fan 2 Drive Fail Band Low Byte Fan 2 Drive Fall Band High Byte
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT
4Ah
R/W
16
8
4
2
1
-
-
-
00h
4Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
8Ah
R/W
16
8
4
2
1
-
-
-
00h
8Bh
R/W
4096
2048
1024
512
256
128
64
32
00h
The Fan Drive Fail Band Registers store the number of tach counts used by the Fan Drive Fail detection circuitry. This circuitry is activated when the fan drive setting high byte is at FFh. When it is enabled, the actual measured fan speed is compared against the target fan speed. These registers are only used when the FSC is active. This circuitry is used to indicate that the target fan speed at full drive is higher than the fan is actually capable of reaching. If the measured fan speed does not exceed the target fan speed minus the Fan Drive Fail Band Register settings for a period of time longer than set by the DRIVE_FAIL_CNTx[1:0] bits then the DRIVE_FAIL status bit will be set and an interrupt generated.
6.33
TACH Target Registers
Table 6.48 TACH Target Registers
ADDR 4Ch 4Dh 8Ch 8Dh
R/W R/W R/W R R/W
REGISTER TACH Target 1 Low Byte TACH Target 1 High Byte TACH Target 2 Low Byte TACH Target 2 High Byte
B7 16 4096 16 4096
B6 8 2048 8 2048
B5 4 1024 4 1024
B4 2 512 2 512
B3 1 256 1 256
B2 128 128
B1 64 64
B0 32 32
DEFAULT F8h FFh F8h FFh
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The TACH Target Registers hold the target tachometer value that is maintained each of the RPM based Fan Speed Control Algorithms. The value in the TACH Target Registers will always reflect the current TACH Target value. If the Look Up Table is active and configured to operate in RPM Mode, then this register will be read only. Writing to this register will have no affect and the data will not be stored. If one of the algorithms is enabled then setting the TACH Target Register to FFh will disable the fan driver (set the fan drive setting to 0%). Setting the TACH Target to any other value (from a setting of FFh) will cause the algorithm to invoke the Spin Up Routine after which it will function normally. The Tach Target is not applied until the high byte is written. Once the high byte is written, the current value of both high and low bytes will be used as the next Tach target. 3
6.34
TACH Reading Registers
Table 6.49 TACH Reading Registers
ADDR 4Eh 4Fh 8Eh 8Fh
R/W R R R R
REGISTER Fan 1 TACH Fan 1 TACH Low Byte Fan 2 TACH Fan 2 TACH Low Byte
B7 4096 16 4096 16
B6 2048 8 2048 8
B5 1024 4 1024 4
B4 512 2 512 2
B3 256 1 256 1
B2 128 128 -
B1 64 64 -
B0 32 32 -
DEFAULT FFh F8h FFh F8h
The TACH Reading Registers' contents describe the current tachometer reading for each of the fan. By default, the data represents the fan speed as the number of 32kHz clock periods that occur for a single revolution of the fan. Equation [5] shows the detailed conversion from TACH measurement (COUNT) to RPM while Equation [6] shows the simplified translation of TACH Reading Register count to RPM assuming a 2-pole fan, measuring 5 edges, with a frequency of 32.768kHz. Whenever the high byte register is read, the corresponding low byte data will be loaded to internal shadow registers so that when the low byte is read, the data will always coincide with the previously read high byte.
where: poles = number of poles of the fan (typically 2) 1(n - 1) RPM = ------------------- x --------------------------------- x f TACH x 60 ( poles ) 1COUNT x ---m fTACH = the tachometer measurement frequency (typically 32.768kHz) n = number of edges measured (typically 5 for a 2 pole fan) m = the multiplier defined by the RANGe bits [6] COUNT = TACH Reading Register value (in decimal) [5]
3,932,160 x m RPM = ------------------------------------COUNT
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6.35
Look Up Table Configuration Registers
Table 6.50 Look Up Table Configuration Registers
ADDR 50h 90h
R/W R/W R/W
REGISTER LUT 1 Configuration LUT2 Configuration
B7 USE_D TS_F1 USE_D TS_F3
B6 USE_D TS_F2 USE_D TS_F4
B5 LUT_L OCK LUT_L OCK
B4 TACH / DRIVE TACH / DRIVE
B3
B2
B1
B0
DEFAULT 00h 00h
TEMP3_CFG [1:0] TEMP3_CFG [1:0]
TEMP4_CFG [1:0] TEMP4_CFG [1:0]
The Look Up Table Configuration Register holds the setup information for the two temperature to fan drive look up tables. Bit 7 - USE_DTS_F1 or USE_DTS_F3 - This bit determines whether the Pushed Temperature 1 or Pushed Temperature 3 registers are using DTS data. `0' (default) - The Pushed Temperature 1 or Pushed Temperature 3 registers are not using DTS data. The contents of these registers are standard 2's complement temperature data. `1' - The Pushed Temperature 1 or Pushed Temperature 3 registers are loaded with DTS data. The contents of these registers are automatically subtracted from a fixed value of 100C before they are compared to the Look Up Table threshold levels. Bit 6 - USE_DTS_F2 or USE_DTS_F4 - This bit determines whether the Pushed Temperature 2 or Pushed Temperature 4 Registers are using DTS data. `0' (default) - The Pushed Temperature 2 or Pushed Temperature 4 registers are not using DTS data. The contents of these registers are standard 2's complement temperature data. `1' - The Pushed Temperature 2 or Pushed Temperature 4 registers are loaded with DTS data. The contents of these registers are automatically subtracted from a fixed value of 100C before they are compared to the Look Up Table threshold levels. Bit 5 - LUT_LOCK - This bit locks updating the Look Up Table entries and determines whether the look up table is being used. `0' (default) - The Look Up Table entries can be updated normally. The Look Up Table will not be used while the Look Up Table entries are unlocked. During this condition, the fan drive output will not change states regardless of temperature or tachometer variation. `1' - The Look Up Table entries are locked and cannot be updated. The Look Up Table is fully active and will be used based on the loaded values. The fan drive output will be updated depending on the temperature and / or TACH variations. APPLICATION NOTE: When the LUT_LOCK bit is set at a logic `0', the fan drive setting will be set at whatever value was last used by the RPM based Fan Speed Control Algorithm or the Look Up Table. Bit 4 - TACH / DRIVEx - This bit selects the data format for the LUT drive settings. `0' (default) - The Look Up Table drive settings are RPM TACH count values for use by the RPM based Fan Speed Control Algorithm. The Look Up Table drive settings should be loaded highest value to lowest value (to coincide with the inversion between TACH counts and actual RPM). `1' - The Look Up Table drive settings are fan drive setting values and are used directly. The drive settings should be loaded lowest value to highest value. APPLICATION NOTE: The TACH / DRIVE bit should be set prior to the LUT_LOCK bit being set so that, if the fan driver is disabled, the output drive is in the proper state. Bits 3-2 - TEMP3_CFG[1:0] - These bits determine the temperature channel that is used for the Temperature 3 inputs to the Look Up Table as shown in Table 6.51.
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Table 6.51 TEMP3_CFG Decode TEMP3_CFG [1:0] 1 0 0 1 1 0 0 1 0 1 TEMPERATURE CHANNEL USED External Diode 3 (default) TRIP_SET / VIN4 Voltage Pushed Temperature 1 (LUT1) Pushed Temperature 3 (LUT2) Reserved
Bits 1-0 - TEMP4_CFG[1:0] - These bits determine the temperature channel that is used for the Temperature 4 inputs to the Look Up Table as shown in Table 6.52.
Table 6.52 TEMP4_CFG Decode TEMP4_CFG [1:0] 1 0 0 1 1 0 0 1 0 1 TEMPERATURE CHANNEL USED Internal Diode (default) External Diode 4 Pushed Temperature 2 (LUT1) Pushed Temperature 4 (LUT2) Reserved
APPLICATION NOTE: When any of the External Diode 1, External Diode 2, and External Diode 3 channels are configured to operate as voltage inputs, the voltage data is used in the Look Up Table instead of the corresponding temperature data. Therefore, the threshold settings must be updated accordingly. All voltage channels (including VIN1, VIN2, and VIN3) are assumed to be increasing (i.e. a larger voltage reading indicates a higher fan speed).
6.36
Look Up Table 1 Registers
Table 6.53 Look Up Table 1 Registers TACH / DRIVE `0' `1' X
ADDR 51h
R/W R/W
REGISTER LUT 1 Drive Setting 1 LUT 1 Ext Diode 1 Setting 1 LUT 1 VIN1 Setting 1
B7 4096 128 -
B6 2048 64 64
B5 1024 32 32
B4 512 16 16
B3 256 8 8
B2 128 4 4
B1 64 2 2
B0 32
DEFAULT FBh
1 1 7Fh (127C) 7Fh (0.4V)
52h
R/W
X
752.9
376.5
188.2
94.12
47.06
23.53
11.76
5.88
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Table 6.53 Look Up Table 1 Registers (continued) TACH / DRIVE
ADDR
R/W
REGISTER LUT 1 Ext Diode 2 Setting 1 LUT 1 VIN2 Setting 1 LUT 1 Temp 3 Setting 1
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 7Fh (0.4V) 7Fh (127C) .. . 92h
X
-
64
32
16
8
4
2
1
53h
R/W
X X
752.9 -
376.5 64
188.2 32
94.12 16
47.06 8
23.53 4
11.76 2
5.88 1
54h
R/W
LUT 1 Voltage 3 Setting 1 LUT 1 Temp 4 Setting 1 ... LUT 1 Drive Setting 8 LUT 1 Ext Diode 1 Setting 8 LUT 1 VIN1 Setting 8 LUT 1 Ext Diode 2 Setting 8 LUT 1 VIN2 Setting 8 LUT 1 Temp 3 Setting 8
X
752.9
376.5
188.2
94.12
47.06
23.53
11.76
5.88
55h ... 74h
R/W ... R/W
X ... `0' `1' X
... 4096 128 -
64 ... 2048 64 64
32 ... 1024 32 32
16 ... 512 16 16
8 ... 256 8 8
4 ... 128 4 4
2 ... 64 2 2
1 ... 32 1 1
7Fh (127C) 7Fh (0.4V) 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 0Ah
75h
R/W
X
752.9
376.5
188.2
94.12
47.06
23.53
11.76
5.88
X
-
64
32
16
8
4
2
1
76h
R/W
X X
752.9 -
376.5 64
188.2 32
94.12 16
47.06 8
23.53 4
11.76 2
5.88 1
77h
R/W
LUT 1 Voltage 3 Setting 8 LUT 1 Temp 4 Setting 8 LUT 1 Temp Hysteresis
X
752.9
376.5
188.2
94.12
47.06
23.53
11.76
5.88
78h 79h
R/W R/W
X X
-
64 -
32 -
16 16
8 8
4 4
2 2
1 1
The Look Up Table 1 Registers hold the 40 entries of the Look Up Table that controls the drive of Fan 1. As the temperature (or voltage) channels are updated, the measured value for each channel is compared against the respective entries in the Look Up Table and the associated drive setting is loaded into an internal shadow register and stored. The bit weighting for temperature inputs represents C and is compared against the measured data. Note that the LUT entry does not include a sign bit. The Look Up Table does not support negative temperature values and the MSBit should not be set for a temperature input. The bit weighting for voltage inputs represents mV above 0V and is compared against the measured data.
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Each temperature (or voltage) channel threshold shares the same hysteresis value. When the measured temperature for any of the channels meets or exceeds the programmed threshold, the drive setting associated with that threshold is used. The temperature must drop below the threshold minus the hysteresis value before the drive setting will be set to the previous value. APPLICATION NOTE: For proper operation, the hysteresis must be smaller than the difference between two consecutive thresholds. If the RPM based Fan Speed Control Algorithm is used, the TACH Target is updated after every conversion. It is always set to the minimum TACH Target that is stored by the Look Up Table. The fan drive setting cycle is updated based on the RPM based Fan Speed Control Algorithm configuration settings. If the RPM based Fan Speed Control Algorithm is not used, then the fan drive setting is updated after every conversion. It is set to the maximum duty cycle that is stored by the Look Up Table.
6.37
Look Up Table 2 Registers
Table 6.54 Look Up Table2 Registers TACH / DRIVE `0' `1' X
ADDR 91h
R/W R/W
REGISTER LUT 2 Drive Setting 1 LUT 2 Ext Diode 1 Setting 1 LUT2 VIN1 Setting 1 LUT 2 Ext Diode 2 Setting 1 LUT2 VIN2 Setting 1 LUT 2 Temp 3 Setting 1
B7 4096 128 -
B6 2048 64 64
B5 1024 32 32
B4 512 16 16
B3 256 8 8
B2 128 4 4
B1 64 2 2
B0 32 1 1
DEFAULT FBh FBh 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 7Fh (0.4V) 7Fh (127C) ... 92h
92h
R/W
X
752.9
376.5
188.2
94.12
47.06
23.53
11.76
5.88
X
-
64
32
16
8
4
2
1
93h
R/W
X X X X ... `0' `1' X
752.9 752.9 ... 4096 128 -
376.5 64 376.5 64 ... 2048 64 64
188.2 32 188.2 32 ... 1024 32 32
94.12 16 94.12 16 ... 512 16 16
47.06 8 47.06 8 ... 256 8 8
23.53 4 23.53 4 ... 128 4 4
11.76 2 11.76 2 ... 64 2 2
5.88 1 5.88 1 ... 32 1 1
94h
R/W LUT2 Voltage 3 Setting 1
95h ... B4h
R/W ... R/W
LUT2 Temp 4 Setting 1 ... LUT 2 Drive Setting 8 LUT 2 Ext Diode 1 Setting 8 LUT2 VIN1 Setting 8
7Fh (127C) 7Fh (0.4V)
B5h
R/W
X
752.9
376.5
188.2
94.12
47.06
23.53
11.76
5.88
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Table 6.54 Look Up Table2 Registers (continued) TACH / DRIVE
ADDR
R/W
REGISTER LUT 2 Ext Diode 2 Setting 8 LUT2 VIN2 Setting 8 LUT 2 Temp 3 Setting 8
B7
B6
B5
B4
B3
B2
B1
B0
DEFAULT 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 7Fh (0.4V) 7Fh (127C) 0Ah
X
-
64
32
16
8
4
2
1
B6h
R/W
X X X X X
752.9 752.9 -
376.5 64 376.5 64 -
188.2 32 188.2 32 -
94.12 16 94.12 16 16
47.06 8 47.06 8 8
23.53 4 23.53 4 4
11.76 2 11.76 2 2
5.88 1 5.88 1 1
B7h
R/W LUT2 Voltage 3 Setting 8
B8h B9h
R/W R/W
LUT2 Temp 4 Setting 8 LUT 2 Temp Hysteresis
The Look Up Table 2 Registers hold the 40 entries of the Look Up Table that controls the drive of Fan 2. As the temperature (or voltage) channels are updated, the measured temperature for each channel is compared against the respective entries in the Look Up Table and the associated drive setting is loaded into an internal shadow register and stored.
6.38
Muxed Pin Configuration Register
Table 6.55 Muxed Pin Configuration Register
ADDR E0h
R/W R/W
REGISTER Muxed Pin Config
B7 PWM1 _EN
B6 GPIO5 _CFG1
B5 GPIO5_ CFG0
B4 GPIO4_ CFG1
B3 GPIO4 _CFG0
B2 GPIO3 _CFG
B1 GPIO2 _CFG
B0 GPIO1 _CFG
DEFAULT 01h
The Muxed Pin Configuration Register controls the pin function for all of the multiple function GPIO pins. Bit 7 - PWM1_EN - Enables the OVERT1# / PWM1 pin as a PWM output. `0' (default) - The OVERT1# / PWM1 pin acts as a dedicated interrupt pin for the External Diode 1 channel. All PWM1 controls will be ignored though can be updated normally. `1' - The OVERT1# / PWM1 pin acts as a PWM output. The High Side Fan Driver will be disabled. Bit 6 - 5 - GPIO5_CFG[1:0] - Determines the pin function for the OVERT3# / GPIO5 / PWM4 pin as shown in Table 6.56. When not configured as a PWM output, all PWM4 controls will be ignored though can be updated normally.
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Table 6.56 GPIO5_CFG[1:0] Decode GPIO5_CFG[1:0] 1 0 0 1 1 0 1 0 1 0 OVERT3# / GPIO5 / PWM4 PIN FUNCTION OVERT3# - the pin will act as a dedicated alert for the External Diode 2 channel (default) GPIO - the pin will act as a GPIO GPIO - the pin will act as a GPIO PWM - the pin will act as a PWM output controlled by the PWM4 Setting Register
Bits 4 - 3 - GPIO4_CFG[1:0] - Determines the pin functions for the OVERT2# / GPIO4 / PWM3 pin as shown in Table 6.57. When not configured as an output, all PWM3 controls will be ignored though can be updated normally.
Table 6.57 GPIO4_CFG[1:0] Decode GPIO4_CFG[1:0] 1 0 0 1 1 0 1 0 1 0 OVERT2# / GPIO4 / PWM3 PIN FUNCTION OVERT2# - the pin will act as a dedicated alert for the External Diode 2 channel (default) GPIO - the pin will act as a GPIO GPIO - the pin will act as a GPIO PWM - the pin will act as a PWM output controlled by the PWM3 Setting Register
Bit 2 - GPIO3_CFG - Determines the pin function for the PWM2 / GPIO3 pin as well as the DAC2 pin. `0' (default) - The PWM2/ GPIO3 pin functions as a PWM output for the 2nd the RPM based Fan Speed Control Algorithm (FSC). The Linear DAC Fan Driver is disabled and the DAC2 pin will be in a high impedance state. `1' - The PWM2 / GPIO3 pin functions as a GPIO. The Linear DAC Fan Driver is enabled and driven by the 2nd RPM based Fan Speed Control Algorithm (FSC). All PWM2 controls will be ignored though are still writable via the SMBus. Bit 1 - GPIO2_CFG - Determines the pin functions for the TACH2 / GPIO2 pin. `0' (default) - The TACH2 / GPIO2 pin functions as a tachometer input for the 2nd the RPM based Fan Speed Control Algorithm (FSC). `1' - The TACH2 / GPIO2 pin functions as a GPIO. When set, the EN_ALGO2 bit will automatically be set to `0' and cannot be set. Bit 0 - GPIO1_CFG - Determines the pin function for the CLK_IN / GPIO1 pin. `0' - The CLK_IN / GPIO1 pin functions as a clock input for the RPM based Fan Speed Control Algorithm (FSC). `1' (default) - The CLK_IN / GPIO1 pin functions as a GPIO.
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6.39
GPIO Direction Register
Table 6.58 GPIO Direction Register
ADDR E1h
R/W R/W
REGISTER GPIO Direction 1
B7 -
B6 -
B5 GPIO 6_DIR
B4 GPIO 5_DIR
B3 GPIO 4_DIR
B2 GPIO 3_DIR
B1 GPIO 2_DIR
B0 GPIO 1_DIR
DEFAULT 00h
The GPIO Direction Register 1 controls the direction of GPIOs 1 through 6. When muxable pins are not configured as a GPIO ports the respective bits are ignored. Bit 5 - 0 - GPIOx_DIR - Controls the input / output state of GPIOs. The bit is not used if the pin is not configured as a GPIO. `0' (default) - The GPIO is configured as an input. `1' - The GPIO is configured as an output.
6.40
GPIO / PWM Pin Output Configuration Register
Table 6.59 GPIO / PWM Pin Output Configuration Register
ADDR
R/W
REGISTER GPIO Output Config
B7
B6 PWM 1_OT
B5 GPIO 6_OT
B4 GPIO 5_OT
B3 GPIO 4_OT
B2 GPIO 3_OT
B1 GPIO 2_OT
B0 GPIO 1_OT
DEFAULT
E2
R/W
-
00h
The GPIO Output Configuration Register controls the output pin type of each GPIO pin. These settings apply to the pin if it is configured as a GPIO output or a PWM. These bits do not apply if the pin is configured as a DAC output or one of the three dedicated OVERTx pins (which are always open drain). Bit 6 - PWM1_OT - Determines the output type for the PWM1 pin. `0' (default) - The PWM1 output is configured as an open drain output (if enabled as a PWM output). `1' - The PWM1 output is configured as a push-pull output (if enabled as an a PWM output). Bit 5 - 0 - GPIOx_OT - Determines the output type for GPIOx. `0' (default) - GPIOx is configured as an open drain output (if enabled as an output). `1' - GPIOxis configured as a push-pull output (if enabled as an output).
6.41
GPIO Input Register
Table 6.60 GPIO Input Register
ADDR E3h
R/W R
REGISTER GPIO Input
B7 -
B6 -
B5 GPIO 6_IN
B4 GPIO 5_IN
B3 GPIO 4_IN
B2 GPIO 3_IN
B1 GPIO 2_IN
B0 GPIO 1_IN
DEFAULT 00h
The GPIO Input Register indicates the state of the corresponding GPIO pin regardless of the functionality of the pin (GPIO, PWM, or TACH) or the direction of the GPIO (input, push-pull output,
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open-drain output). When a GPIO is configured as an input, any change of state will assert the ALERT# pin (unless GPIO interrupts are masked, see Section 6.15).
6.42
GPIO Output Register
Table 6.61 GPIO Output Register
ADDR E4h
R/W R/W
REGISTER GPIO Output 1
B7 -
B6 -
B5 GPIO6_ OUT
B4 GPIO5_ OUT
B3 GPIO4_ OUT
B2 GPIO3 _OUT
B1 GPIO2 _OUT
B0 GPIO1 _OUT
DEFAULT 00h
The GPIO Output Register controls the state of the corresponding GPIO pins when they areconfigured as GPIOs and as outputs. If the output is configured as an open-drain output, then it requires a pull-up resistor to VDD. Setting the corresponding bit to a `1' will act to disable the output allowing the pull-up resistor to pull the output high. Setting the corresponding bit to a `0' will enable the output and drive the pin to a logical `0' state. If the output is configured as a push-pull output, then output pin will immediately be driven to match the corresponding bit setting.
6.43
GPIO Interrupt Enable Register
Table 6.62 GPIO Interrupt Enable Register
ADDR
R/W
REGISTER GPIO Interrupt Enable
B7
B6
B5 GPIO6_ INT_EN
B4 GPIO5_ INT_EN
B3 GPIO4_ INT_EN
B2 GPIO3_ INT_EN
B1 GPIO2_ INT_EN
B0 GPIO1_ INT_EN
DEFAULT
E5h
R/W
-
-
00h
The GPIO Interrupt Enable Register enables the GPIOs to assert the ALERT pin when they change state. When the GPIO pins are disabled or configured as outputs, then these bits are ignored. Bit 5 - 0 - GPIOx_INT_EN - Allows the ALERT# pin to be asserted when the GPIOx pin changes state (when configured as an input). `0' (default) - The ALERT# pin will not be asserted when the GPIOx pin changes state (when configured as an input). `1' - The ALERT# pin will be asserted when the GPIOxpin changes state (when configured as an input).
6.44
GPIO Status Register
Table 6.63 GPIO Status Register
ADDR E6h
R/W R-C
REGISTER GPIO Status
B7 -
B6 -
B5 GPIO6_ STS
B4 GPIO5_ STS
B3 GPIO4_ STS
B2 GPIO3_ STS
B1 GPIO2_ STS
B0 GPIO1_ STS
DEFAULT 00h
The GPIO Status Register indicates which GPIO has changed states to cause the ALERT pins to be asserted. This register is cleared when it is read. The bits in this register are set whenever the
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corresponding GPIO changes states regardless if the ALERT pins are asserted. Once a bit is set, it will remain set until read. If any bit in this register is set, then the GPIO status bit will be set. Bit 5 - 0 - GPIOx_STS - Indicates that the GPIOx pin has changed states from a `0' to a `1' or a `1' to a `0' (when configured as a GPIO input).
6.45
Software Lock Register
Table 6.64 Software Lock Register
ADDR EFh
R/W R/W
REGISTER Software Lock
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1 -
B0 LOCK
DEFAULT 00h
The Software Lock Register controls the software locking of critical registers. This register is software locked. Bit 0 - LOCK - this bit acts on all registers that are designated SWL. When this bit is set, the locked registers become read only and cannot be updated. `0' (default) - all SWL registers can be updated normally. `1' - all SWL registers cannot be updated and a hard-reset is required to unlock them.
6.46
Product Features Register
Table 6.65 Product Features Register
ADDR FCh
R/W R
REGISTER Product Features
B7 -
B6 -
B5 -
B4 -
B3 -
B2 -
B1
B0
DEFAULT 00h
SHDN_SEL[1:0]
The Product Features Register indicates which pin selected functionality is enabled. Bit 1 - 0 - SHDN_SEL[1:0] - Indicates what the detected pin state of the SHDN_SEL pin was and which functions are enabled.
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Table 6.66 SHDN_SEL Bit Decode FUN_SEL[1:0] 1 0 EXTERNAL DIODE 1 MODE Transistor mode - Beta = automatic REC = enabled Diode mode Beta = 1111b REC = disabled Not used Internal diode linked to Hardware Thermal / Critical Shutdown circuitry CRITICAL / THERMAL SHUTDOWN TEMPERATURE RANGE
VIN4 OR TRIP_SET
0
0
High range - 92C to 154C
TRIP_SET
0
1
Low Range 60C to 122C
TRIP_SET
1
0
Low Range 60C to 122C
TRIP_SET or VIN4 (see Section 6.1.2)
6.47
Product ID Register
Table 6.67 Product ID Register
ADDR FDh
R/W R
REGISTER Product ID Register
B7 0
B6 0
B5 0
B4 1
B3 1
B2 1
B1 1
B0 0
DEFAULT 1Eh
The Product ID Register contains a unique 8 bit word that identifies the product.
6.48
Manufacturer ID Register
Table 6.68 Manufacturer ID Register
ADDR FEh
R/W R
REGISTER Manufacturer ID
B7 0
B6 1
B5 0
B4 1
B3 1
B2 1
B1 0
B0 1
DEFAULT 5Dh
The Manufacturer ID Register contains a 8 bit word that identifies SMSC.
6.49
Revision Register
Table 6.69 Revision Register
ADDR FFh
R/W R
REGISTER Revision
B7 0
B6 0
B5 0
B4 0
B3 0
B2 0
B1 1
B0 0
DEFAULT 02h
The Revision Register contains a 8 bit word that identifies the die revision.
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Chapter 7 Package Drawing
7.1 QFN 28-pin 5mm x 5mm
Figure 7.1 EMC2106 28-Pin 5x5mm QFN Package Outline and Parameters
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Appendix A Thermistors
The EMC2106 can monitor thermistor inputs on the TRIP_SET / VIN4 as well as supporting a thermistor option on the all of the external diode pins pairs (DP1 / VREF_T1 and DN1 / VIN1,etc.). The Thermistors can be connected as shown in Figure A.1. Figure A.1 is representative of one of the thermistor channels and will apply to DP1 / VREF_T1 and DN1 / VIN1, DP2 / VREF_T2 and DN2 / VIN2. The top side resistor is internally integrated in the case of the TRIP_SET / VIN4 channel and the VREF voltage will not be brought out externally. The Thermistor should be connected in the same way as RSET.
EMC2104/5/6
DP3 / DN4 / VREF_T3
Buffer Reference Voltage
1.2K 1%
DN3 / DP4 / VIN3
ADC
10K 1% Thermistor
0.1uF
Figure A.1 "Low Side" Thermistor Connection The relationship between voltage and temperature is roughly linear. the measured voltage by the EMC2106 will be inversely proportional to temperature . Linearization methods can only accurately capture the temperature over a limited window of temperatures. For a 10k Ohm type 3370 Thermistor and a 1.2k ohm 1% setting resistor, the output response corresponding to a thermistor is tabulated in Table A.1. If the INV_VINx bit is set then the results of the circuit (configured as shown in Figure A.1) is shown in Table A.2. The EMC2106 does not perform any numerical calculations on the thermistor value if a thermistor is monitored on TRIP_SET / VIN4 pin. If the External Diode 1, External Diode 2, or External Diode 3 channels are configured to measure a thermistor, it must be configured as shown in Figure A.1. When measuring a thermistor input with Fan Control Look Up Table, care must be taken that the temperature thresholds are entered as a unsigned voltage number that corresponds to the desired thermal threshold. Also note that the LUT assumes that the VIN1 and TRIP_SET / VIN4 voltage inputs are directly proportional to temperature.
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A.1
Thermistor Look Up Tables
Table A.1 "Low Side" Thermistor Look Up Table
T (C) -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16
ADC CODE 254 253 253 253 253 253 253 253 252 252 252 252 252 252 252 252 251 251 251 251 251 251 250 250 250 250 250 249 249 249
T (C) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44
ADC CODE 235 235 234 233 232 231 231 230 229 228 227 226 225 224 223 222 221 220 219 218 217 216 215 213 212 211 210 208 207 206
92
T (C) 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104
ADC CODE 157 155 154 152 150 148 146 145 143 141 139 138 136 135 133 131 129 128 126 124 123 121 119 118 116 114 113 111 110 108
T (C) 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164
ADC CODE 72 71 70 69 68 67 66 65 64 63 62 61 60 59 59 58 57 56 55 54 54 53 52 51 51 50 49 48 48 47
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Table A.1 "Low Side" Thermistor Look Up Table (continued) T (C) -15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADC CODE 249 248 248 248 247 247 247 246 246 246 245 245 245 244 244 243 243 243 242 242 241 241 240 240 239 238 238 237 237 236 T (C) 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 ADC CODE 205 203 202 200 199 198 196 195 193 192 190 189 187 185 184 182 181 179 177 176 174 172 171 169 167 166 164 162 160 159 T (C) 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 ADC CODE 106 105 103 102 100 99 97 96 95 93 92 90 89 88 86 85 84 82 81 80 79 82 81 80 78 77 76 75 74 73 T (C) 165 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 ADC CODE 46 46 45 44 44 43 43 42 41 41 40 40 39 38 38 37 37 36 36 35 35 34 34 33 33 32 32
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Table A.2 Inverted Thermistor Look Up Table T (C) -45 -44 -43 -42 -41 -40 -39 -38 -37 -36 -35 -34 -33 -32 -31 -30 -29 -28 -27 -26 -25 -24 -23 -22 -21 -20 -19 -18 -17 -16 -15 ADC CODE 0 1 1 1 1 1 1 1 2 2 2 2 2 2 2 2 3 3 3 3 3 3 4 4 4 4 4 5 5 5 5 T (C) 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 ADC CODE 19 20 20 21 22 23 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 41 42 43 44 46 47 48 50
94
T (C) 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105
ADC CODE 97 99 100 102 104 106 108 109 111 113 115 116 118 120 121 123 125 126 128 130 131 133 135 136 138 140 141 143 144 146 148
T (C) 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165
ADC CODE 182 183 184 185 186 187 188 189 190 191 192 193 194 195 195 196 197 198 199 200 200 201 202 203 203 204 205 206 206 207 208
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Table A.2 Inverted Thermistor Look Up Table (continued) T (C) -14 -13 -12 -11 -10 -9 -8 -7 -6 -5 -4 -3 -2 -1 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 ADC CODE 6 6 6 7 7 7 8 8 8 9 9 9 10 10 11 11 11 12 12 13 13 14 15 15 16 16 17 18 18 T (C) 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 ADC CODE 51 52 54 55 56 58 59 61 62 64 65 67 69 70 72 73 75 77 78 80 82 83 85 87 88 90 92 94 95 T (C) 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 ADC CODE 149 151 152 154 155 157 158 159 161 162 164 165 166 168 169 170 172 173 174 175 172 173 174 176 177 178 179 180 181 T (C) 166 167 168 169 170 171 172 173 174 175 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 ADC CODE 208 209 210 210 211 211 212 213 213 214 214 215 216 216 217 217 218 218 219 219 220 220 221 221 222 222
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Appendix B Look Up Table Operation
The EMC2106 uses a look-up table to apply a user-programmable fan control profile based on measured temperature to each fan driver. In this look-up table, each temperature channel is allowed to control the fan drive output independently (or jointly) by programming up to eight pairs of temperature and drive setting entries. The user programs the look-up table based on the desired operation. If the RPM based Fan Speed Control Algorithm is to be used (see Section 6.6), then the user must program an RPM target for each temperature setting of interest. Alternately, if the RPM based Fan Speed Control Algorithm is not to be used, then the user must program a drive setting for each temperature setting of interest. If the measured temperature on the External Diode channel meets or exceeds any of the temperature thresholds for any of the channels, the fan output will be automatically set to the desired setting corresponding to the exceeded temperature. In cases where multiple temperature channel thresholds are exceeded, the highest fan drive setting will take precedence. When the measured temperature drops to a point below a lower threshold minus the hysteresis value, the fan output will be set to the corresponding lower set point. The following sections show examples of how the Look Up Table is used and configured. Each Look Up Table Example uses the Fan 1 Look Up Table Registers configured as shown in Table B.1.
Table B.1 Look Up Table Format STEP 1 2 3 4 5 6 7 8 TEMP 1 LUT Temp 1 Setting 1 (52h) LUT Temp 1 Setting 2 (57h) LUT Temp 1 Setting 3 (5Ch) LUT Temp 1 Setting 4 (61h) LUT Temp 1 Setting 5 (66h) LUT Temp 1 Setting 6 (6Bh) LUT Temp 1 Setting 7 (70h) LUT Temp 1 Setting 8 (75h) TEMP 2 LUT Temp 2 Setting 1 (53h) LUT Temp 2 Setting 2 (58h) LUT Temp 2 Setting 3 (5Dh) LUT Temp 2 Setting 4 (62h) LUT Temp 2 Setting 5 (67h) LUT Temp 2 Setting 6 (6Ch) LUT Temp 2 Setting 7 (71h) LUT Temp 2 Setting 8 (76h) TEMP 3 LUT Temp 3 Setting 1 (54h) LUT Temp 3 Setting 2 (59h) LUT Temp 3 Setting 3 (5Eh) LUT Temp 3 Setting 4 (63h) LUT Temp 3 Setting 5 (68h) LUT Temp 3 Setting 6 (6Dh) LUT Temp 3 Setting 7 (72h) LUT Temp 3 Setting 8 (77h) TEMP 4 LUT Temp 4 Setting 1 (55h) LUT Temp 4 Setting 2 (5Ah) LUT Temp 4 Setting 3 (5Fh) LUT Temp 4 Setting 4 (64h) LUT Temp 4 Setting 5 (69h) LUT Temp 4 Setting 6 (6Eh) LUT Temp 4 Setting 7 (73h) LUT Temp 4 Setting 8 (78h) LUT DRIVE LUT Drive Setting 1 (51h) LUT Drive Setting 2 (56h) LUT Drive Setting 3 (5Bh) LUT Drive Setting 4 (60h) LUT Drive Setting 5 (65h) LUT Drive Setting 6 (6Ah) LUT Drive Setting 7 (6Fh) LUT Drive Setting 8 (74h)
B.1
Example #1
This example does not use the RPM based Fan Speed Control Algorithm. Instead, the Look Up Table is configured to directly set a fan drive setting based on the temperature of four of its measured inputs. The configuration is set as shown in Table B.2. Once configured, the Look Up Table is loaded as shown in Table B.3. Table B.3 shows three temperature configurations using the settings in Table B.3 and the final fan drive setting that the Look Up Table will select.
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Table B.2 Look Up Table Example #1 Configuration ADDR REGISTER LUT 1 Configuration B7 USE_D TS_F1 0 B6 USE_D TS_F2 0 B5 LUT_L OCK 1 B4 TACH / DRIVE 1 B3 B2 B1 B0 SETTING
50h
TEMP3_CFG [1:0] 0 0
TEMP4_CFG [1:0] 0 0
C0h
Table B.3 Fan Speed Control Table Example #1 EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40
oC
FAN SPEED STEP # 1 2 3 4 5 6 7 8
EXTERNAL DIODE 2 TEMPERATURE (GPU) 60oC 70oC 75oC 80oC 85oC 90oC 95oC 100oC
EXTERNAL DIODE 3 TEMPERATURE (SKIN) 30oC 35oC 40oC 45oC 50oC 55oC 60oC 65oC
INTERNAL DIODE TEMPERATURE (AMBIENT) 40oC 45oC 50oC 55oC 60oC 65oC 70oC 75oC
FAN DRIVE SETTINGS 0% 30% 40% 50% 60% 70% 80% 100%
50oC 60oC 70oC 80oC 90oC 100oC
Note: The values shown in Table B.3 are example settings. All the cells in the look-up table are programmable via SMBus.
Table B.4 Fan Speed Determination for Example #1 (using settings in Table B.3) EXTERNAL DIODE 1 TEMPERATURE (CPU) Example 1: Example 2: Example 3: EXTERNAL DIODE 2 TEMPERATURE (GPU) 82C
EXTERNAL DIODE 3 TEMPERATURE (SKIN) 48C
INTERNAL DIODE TEMPERATURE (AMBIENT) 58C 58C
FAN DRIVE SETTING RESULT 70% (CPU temp requires highest drive) 80% (GPU and Skin require highest drive) 100% (Internal temp requires highest drive)
82C
82C 82C
97C
97C
62C
62C
75C
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B.2
Example #2
This example uses the RPM based Fan Speed Control Algorithm. The Spin Level (used by the Spin Up Routine) should be changed to 50% drive for a total Spin Time of 1 second. For all other RPM configuration settings, the default conditions are used. For control inputs, it uses the External Diode 1 channel normally, a thermistor input on the External Diode 2 channel, the internal diode channel, and a Pushed Temperature that represents the MCU temperature in standard format. The configuration is set as shown in Table B.5 while Table B.6 shows how the table is loaded. Note that when using Thermistor data, the VIN2_INV bit should be set. The circuitry will automatically subtract the measured thermistor voltage from a quantity of FFh (effectively inverting it). Therefore, the Look Up Table is loaded with ascending voltage thresholds with respect to the drive settings. Additionally, the reading register will show this same value (subtracted from FFh).
Table B.5 Look Up Table Example #2 Configuration ADDR REGISTER Configuration 3 Fan 1 Configuration 1 Fan 1 Spin Up Configuration EN_ ALGO 1 B7 B6 VIN4_I NV 0 B5 VIN3_E N 0 B4 VIN3_I NV 0 B3 VIN2_ EN 1 B2 VIN2_I NV 1 B1 VIN1_ EN 0 B0 VIN1_I NV 0 SETTING
22h
0Ch
RANGE[1:0] 1 0 NOKICK 1 0 LUT_LO CK 1
EDGES[1:0] 0 1 SPIN_LVL[2:0] 0 TACH / DRIVE 0 1 0 0
UPDATE[2:0] CBh 1 1
42h
46h
DRIVE_FAIL_CNT 1 [1:0] 0 USE_D TS_F1 0 0 USE_D TS_F2 0
SPINUP_TIME [1:0] 1 0
0Ah
50h
LUT 1 Configuration
TEMP3_CFG [1:0] 1 0
TEMP4_CFG [1:0] 0 0
28h
Table B.6 Fan Speed Control Table Example #2 FAN SPEED STEP # 1 2 3 4 5 EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40oC 50oC 60oC 70oC THERMISTOR 2 VOLTAGE READING 156.25mV (45C) 178.125mV (50C) 203.125mV (55C) 228.125mV (60C) 253.125mV (65C) PUSHED TEMPERATURE SETTING 30oC 35oC 40oC 45oC 50oC INTERNAL DIODE TEMPERATURE (AMBIENT) 40oC 45oC 50oC 55oC 60oC
TACH TARGET 3Dh (1007 RPM) 1Eh (2048 RPM) 14h (3072 RPM) 0Fh (4096 RPM) 0Ch (5120 RPM)
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Table B.6 Fan Speed Control Table Example #2 (continued) FAN SPEED STEP # 6 7 8 EXTERNAL DIODE 1 TEMPERATURE (CPU) 80oC 90oC 100oC THERMISTOR 2 VOLTAGE READING 278.125mV (70C) 306.25mV (75C) 334.375mV (80C) PUSHED TEMPERATURE SETTING 55oC 60oC 65oC INTERNAL DIODE TEMPERATURE (AMBIENT) 65oC 70oC 75oC
TACH TARGET 0Ah (6144 RPM) 09h (6826 RPM) 08h (7680 RPM)
Note: The values shown in Table B.6 are example settings. All the cells in the look-up table are programmable via SMBus.
Table B.7 Fan Speed Determination for Example #2 (using settings in Table B.6) EXTERNAL DIODE 1 TEMPERATURE (CPU)
THERMISTOR 2 VOLTAGE READING
PUSHED TEMPERATURE
INTERNAL DIODE TEMPERATURE (AMBIENT)
FAN DRIVE SETTING RESULT 0Ch (5120RPM) CPU requires highest target 09h (6826 RPM) Thermistor requires highest target 09h (6826 RPM) Pushed Temperature requires highest target
Example 1:
75C
140.375mV
48C
58C
Example 2:
75C
310mV
58C
58C
Example 3:
75C
235.125mV
62C
58C
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B.3
Example #3
This example uses the RPM based Fan Speed Control Algorithm. The Spin Level (used by the Spin Up Routine) should be changed to 50% drive for a total Spin Time of 1 second. For all other RPM configuration settings, the default conditions are used. For control inputs, it uses the External Diode 1 channel normally, the External Diode 2 channel normally, and both Pushed Temperature registers in DTS format. The configuration is set as shown in Table B.8 while Table B.9 shows how the table is loaded. Note that when using DTS data, the USE_DTS_F1 and / or USE_DTS_F2 bits should be set. The Pushed Temperature Registers are loaded with the normal DTS values as received by the processor. When the DTS value is used by the Look Up Table, the value that is stored in the Pushed Temperature Register is subtracted from a fixed temperature of 100C. This resultant value is then compared against the Look Up Table thresholds normally. When programming the Look Up Table, it is necessary to take this translation into account else incorrect settings may be selected.
Table B.8 Look Up Table Example #3 Configuration ADDR REGISTER Fan 1 Configuration 1 Fan 1 Spin Up Configuration B7 EN_ ALGO 1 B6 B5 B4 B3 B2 B1 UPDATE[2:0] CBh 1 0 NOKICK 1 0 LUT_LO CK 1 0 TACH / DRIVE 0 0 1 SPIN_LVL[2:0] 1 0 0 1 1 B0 SETTING
RANGE[1:0]
EDGES[1:0]
42h
46h
DRIVE_FAIL_CNT 1 [1:0] 0 USE_D TS_F1 1 0 USE_D TS_F2 1
SPINUP_TIME [1:0] 1 0
0Ah
50h
LUT 1 Configuration
TEMP3_CFG [1:0] 1 0
TEMP4_CFG [1:0] 1 0
EAh
Table B.9 Fan Speed Control Table Example #3 EXTERNAL DIODE 2 TEMPERATURE (GPU) 65oC 75oC 85oC 90oC 95oC 100oC
FAN SPEED STEP # 1 2 3 4 5 6
EXTERNAL DIODE 1 TEMPERATURE (CPU) 35oC 40oC 50oC 60oC 70oC 80oC
PUSHED TEMPERATURE SETTING (DTS1) 50oC 55oC 60oC 65oC 70oC 75oC
PUSHED TEMPERATURE SETTING (DTS2) 40oC 45oC 50oC 55oC 60oC 65oC
TACH TARGET 3Dh (1007 RPM) 1Eh (2048 RPM) 14h (3072 RPM) 0Fh (4096 RPM) 0Ch (5120 RPM) 0Ah (6144 RPM)
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Table B.9 Fan Speed Control Table Example #3 (continued) EXTERNAL DIODE 2 TEMPERATURE (GPU) 105oC 110oC
FAN SPEED STEP # 7 8
EXTERNAL DIODE 1 TEMPERATURE (CPU) 90oC 100oC
PUSHED TEMPERATURE SETTING (DTS1) 80oC 85oC
PUSHED TEMPERATURE SETTING (DTS2) 80oC 100oC
TACH TARGET 09h (6826 RPM) 08h (7680 RPM)
Note: The values shown in Table B.9 are example settings. All the cells in the look-up table are programmable via SMBus.
Table B.10 Fan Speed Determination for Example #3 (using settings in Table B.9) EXTERNAL DIODE 1 TEMPERATURE (CPU) EXTERNAL DIODE 2 TEMPERATURE (GPU)
PUSHED TEMPERATURE (DTS1) 35C (translated as 65C)
PUSHED TEMPERATURE (DTS2) 50C (translated as 50C) 20C (translated as 80C)
FAN DRIVE SETTING RESULT 0Ch (5120 RPM) CPU requires highest target 08h (7680 RPM) DTS1 requires highest target 09h (6826 RPM) DTS2 requires highest target
Example 1:
75C
75C
Example 2:
75C
90C
15C (translated as 85C)
30C (translated as 70C)
Example 3:
75C
97.25C
5C (translated as 95C)
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Appendix C RPM to Tachometer Count Look Up Table
C.1 1k RPM Range
The Look Up Table is an example based on the assumption that the fan being measured has 2-poles and is meausring 5 edges using the 1k RPM range settings. The data presented in the reading is only the high byte data and the decimal count value only represents high byte data.
Table C.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) REGISTER READING (HEX) 80 81 82 83 84 85 86 87 88 89 8A 8B 8C 8D 8E 8F 90 91 92 93 94 95 96 97 98
TACH COUNT (DECIMAL) 0 32 64 96 128 160 192 224 256 288 320 352 384 416 448 480 512 544 576 608 640 672 704 736 768
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REGISTER READING (HEX) 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18
FAN SPEED (RPM) Disabled 245760 122880 81920 61440 49152 40960 35109 30720 27307 24576 22342 20480 18905 17554 16384 15360 14456 13653 12935 12288 11703 11171 10685 10240
102
TACH COUNT (DECIMAL) 4096 4128 4160 4192 4224 4256 4288 4320 4352 4384 4416 4448 4480 4512 4544 4576 4608 4640 4672 4704 4736 4768 4800 4832 4864
FAN SPEED (RPM) 1920 1905 1890 1876 1862 1848 1834 1820 1807 1794 1781 1768 1755 1743 1731 1719 1707 1695 1683 1672 1661 1649 1638 1628 1617
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Table C.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) 99 9A 9B 9C 9D 9E 9F A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 AA AB AC AD AE AF B0 B1 B2 B3 B4 B5 B6 B7 B8
TACH COUNT (DECIMAL) 800 832 864 896 928 960 992 1024 1056 1088 1120 1152 1184 1216 1248 1280 1312 1344 1376 1408 1440 1472 1504 1536 1568 1600 1632 1664 1696 1728 1760 1792
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REGISTER READING (HEX) 19 1A 1B 1C 1D 1E 1F 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 38
FAN SPEED (RPM) 9830 9452 9102 8777 8474 8192 7928 7680 7447 7228 7022 6827 6642 6467 6302 6144 5994 5851 5715 5585 5461 5343 5229 5120 5016 4915 4819 4726 4637 4551 4468 4389
103
TACH COUNT (DECIMAL) 4896 4928 4960 4992 5024 5056 5088 5120 5152 5184 5216 5248 5280 5312 5344 5376 5408 5440 5472 5504 5536 5568 5600 5632 5664 5696 5728 5760 5792 5824 5856 5888
FAN SPEED (RPM) 1606 1596 1586 1575 1565 1555 1546 1536 1526 1517 1508 1499 1489 1480 1472 1463 1454 1446 1437 1429 1421 1412 1404 1396 1388 1381 1373 1365 1358 1350 1343 1336
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Table C.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) B9 BA BB BC BD BE BF C0 C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 D2 D3 D4 D5 D6 D7
TACH COUNT (DECIMAL) 1824 1856 1888 1920 1952 1984 2016 2048 2080 2112 2144 2176 2208 2240 2272 2304 2336 2368 2400 2432 2464 2496 2528 2560 2592 2624 2656 2688 2720 2752 2784
REGISTER READING (HEX) 39 3A 3B 3C 3D 3E 3F 40 41 42 43 44 45 46 47 48 49 4A 4B 4C 4D 4E 4F 50 51 52 53 54 55 56 57
FAN SPEED (RPM) 4312 4237 4165 4096 4029 3964 3901 3840 3781 3724 3668 3614 3562 3511 3461 3413 3367 3321 3277 3234 3192 3151 3111 3072 3034 2997 2961 2926 2891 2858 2825
TACH COUNT (DECIMAL) 5920 5952 5984 6016 6048 6080 6112 6144 6176 6208 6240 6272 6304 6336 6368 6400 6432 6464 6496 6528 6560 6592 6624 6656 6688 6720 6752 6784 6816 6848 6880
FAN SPEED (RPM) 1328 1321 1314 1307 1300 1293 1287 1280 1273 1267 1260 1254 1248 1241 1235 1229 1223 1217 1211 1205 1199 1193 1187 1182 1176 1170 1165 1159 1154 1148 1143
Revision 1.72 (11-01-07)
104
SMSC EMC2106
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
Datasheet
Table C.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) D8 D9 DA DB DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7
TACH COUNT (DECIMAL) 2816 2848 2880 2912 2944 2976 3008 3040 3072 3104 3136 3168 3200 3232 3264 3296 3328 3360 3392 3424 3456 3488 3520 3552 3584 3616 3648 3680 3712 3744 3776 3808
SMSC EMC2106
REGISTER READING (HEX) 58 59 5A 5B 5C 5D 5E 5F 60 61 62 63 64 65 66 67 68 69 6A 6B 6C 6D 6E 6F 70 71 72 73 74 75 76 77
FAN SPEED (RPM) 2793 2761 2731 2701 2671 2643 2614 2587 2560 2534 2508 2482 2458 2433 2409 2386 2363 2341 2318 2297 2276 2255 2234 2214 2194 2175 2156 2137 2119 2101 2083 2065
105
TACH COUNT (DECIMAL) 6912 6944 6976 7008 7040 7072 7104 7136 7168 7200 7232 7264 7296 7328 7360 7392 7424 7456 7488 7520 7552 7584 7616 7648 7680 7712 7744 7776 7808 7840 7872 7904
FAN SPEED (RPM) 1138 1133 1127 1122 1117 1112 1107 1102 1097 1092 1087 1083 1078 1073 1069 1064 1059 1055 1050 1046 1041 1037 1033 1028 1024 1020 1016 1011 1007 1003 999 995
Revision 1.72 (11-01-07)
DATASHEET
Dual RPM-Based Linear Fan Controller with Hardware Thermal Shutdown
Datasheet
Table C.1 Tachometer Count to RPM Look Up Table (Range = 1000 RPM) (continued) REGISTER READING (HEX) F8 F9 FA FB FC FD FE FF
TACH COUNT (DECIMAL) 3840 3872 3904 3936 3968 4000 4032 4064
REGISTER READING (HEX) 78 79 7A 7B 7C 7D 7E 7F
FAN SPEED (RPM) 2048 2031 2014 1998 1982 1966 1950 1935
TACH COUNT (DECIMAL) 7936 7968 8000 8032 8064 8096 8128 8160
FAN SPEED (RPM) 991 987 983 979 975 971 968 964
Revision 1.72 (11-01-07)
106
SMSC EMC2106
DATASHEET

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